Semiconductor Package With 3D Solenoid Inductor for Lower Resistance
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Solution Overview
Problem
The integration of smaller semiconductor components requires smaller packages that efficiently utilize area, and existing inductors in semiconductor packages face limitations due to high resistance, which reduces their performance as measured by the Q factor.
Innovation Solution
The integration of a 3D solenoid inductor within the semiconductor package, formed from portions of the metallization patterns of the redistribution and die stack structures, including through vias for electrical connection, enhances the inductor's performance by reducing resistance and increasing the Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar inductor design is used in semiconductor packages, then the package area is reduced, but the resistance increases and Q factor decreases
Solution Approach 1:
The patent transitions from traditional planar (2D) inductor designs to three-dimensional solenoid inductor structures. By utilizing vertical stacking and 3D routing of conductive paths through multiple metal layers and via connections, the inductor achieves higher inductance values and lower resistance within the same package footprint, directly resolving the contradiction between area reduction and resistance loss.
Solution Approach 2:
The 3D solenoid inductor structure embeds multiple conductive loops and routing paths within each other in vertical space. The inductor utilizes nested metal layers where conductive traces are stacked vertically and connected through via holes, creating a compact solenoid configuration that maximizes inductance while minimizing the horizontal package area.
2Productivity
If smaller semiconductor components are integrated, then integration density increases, but package area utilization becomes more constrained
Solution Approach 1:
As integration density increases and horizontal space becomes constrained, the patent employs vertical dimensionality to accommodate inductor structures. By routing conductive paths through multiple metal layers stacked vertically and connecting them via via holes, the design achieves high integration density while maintaining adequate inductor performance within limited package area.
Solution Approach 2:
The patent integrates the inductor structure with the existing redistribution circuit metallization layers. The inductor conductive paths are formed using the same metal layers and via structures that serve the redistribution function, merging two functions into a single integrated structure that optimizes both signal routing and inductance without requiring additional dedicated space.
3Loss of energy
If inductor resistance is reduced to improve Q factor, then energy loss decreases, but manufacturing complexity increases
Solution Approach 1:
The patent merges the inductor conductive paths with the redistribution circuit metallization layers already present in the semiconductor package. By forming inductor traces using the same metal deposition and patterning processes as the redistribution layers, and utilizing existing via structures for connections, the design reduces energy loss through optimized current paths without significantly increasing manufacturing complexity beyond the standard multi-layer interconnect fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D solenoid inductor design improves the efficiency and performance of semiconductor packages by increasing the Q factor, enabling better energy storage and reducing energy loss.
Implementation Method 1
An inductor is embedded in the redistribution structure and the interconnect structure
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.