Semiconductor Package Miniaturization via 3D Stacking and Nesting

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Solution Overview

Problem

The electronics industry faces challenges in miniaturizing semiconductor packages while maintaining high integration and performance, leading to increased manufacturing costs due to the need for cost-effective solutions that enable high-density system integration in a single package.

Innovation Solution

The semiconductor package design incorporates a substrate with multiple pads, conductive elements, surface mount devices, bonding wires, and a heat-sink, along with via-plugs and solder resistance layers to facilitate miniaturization and enhance design flexibility by allowing for additional components and improved electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If high integration is implemented to achieve high-density system integration in a single package, then the integration performance is improved, but the manufacturing cost increases

Engineering Contradiction:

Improveintegration performanceVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple device components including semiconductor die, surface mount devices, and interconnection structures into a single integrated package substrate. This merging approach achieves high-density system integration while using standardized manufacturing processes to control costs.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The package substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, thermal management pathways, and mounting surfaces for various components. This multi-functionality reduces the need for separate structures, lowering overall manufacturing complexity and cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If the package size is reduced to achieve miniaturization, then the compactness is improved, but the area for additional elements is reduced

Engineering Contradiction:

Improvepackage sizeVSAvoidarea for additional elements

Core Design Contradiction:

Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent utilizes three-dimensional vertical stacking and multi-layer substrate structures to accommodate additional elements. By transitioning from two-dimensional lateral arrangement to three-dimensional vertical integration, the design achieves miniaturization while preserving space for extra components through vertical layering.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The design embeds smaller components and interconnection structures within the package substrate layers, creating a nested configuration where conductive elements, vias, and surface mount devices are integrated within the substrate thickness rather than occupying additional lateral space.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Area of stationary object

If multiple device components are integrated in a single semiconductor package to reduce size, then the package compactness is improved, but the device complexity increases

Engineering Contradiction:

Improvepackage sizeVSAvoidstructure complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent divides the integrated package into distinct functional layers and modules, including separate substrate layers, conductive element groups, and component mounting areas. This segmentation allows each layer to be optimized independently and simplifies the manufacturing process by enabling modular assembly, thereby reducing overall structural complexity despite high integration.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design facilitates the miniaturization of IC packages, increases the area for additional elements, and enhances design flexibility, thereby reducing manufacturing costs and improving the integration of high-density systems.

Implementation Method 1

The heat-sink is mounted on the substrate and has at least one cavity to accommodate the first pad, the second pad, a portion of the first conductive element, the bonding wire and the surface mount device

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The solder resistance layer covers a portion of the first bonding area and a portion of the second bonding area

Methodology Applied

Scientific EffectSolder resistance:

Implementation Method 3

The first bonding wire electrically connects a first bonding area of the first conductive element with a second bonding area of the first pad

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9806053B2Semiconductor package

Publication Date: 2017.10.31 HAMILCAR BARCA IP LLC

AI summary

A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate has a first top surface. The first conductive layer is formed on the first top surface and has a first conductive element and a second conductive element separated from each other. The first SMD is mounted on the first top surface, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.