Semiconductor Package With 3D Trench Capacitors for High Capacitance Density
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving smaller sizes and higher integration densities, particularly with integrated passive devices, due to limitations in capacitance density and manufacturing processes that lead to void formation and reduced electrode surface area.
Innovation Solution
The implementation of a 3D trench capacitor structure, where 2D trench capacitors are connected in parallel across multiple device layers, increasing capacitance density by enhancing the depth of trench segments and using fusion bonding to mitigate alignment issues in hybrid bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D trench capacitor structures are used, then manufacturing process is simpler, but capacitance density is limited and footprint is larger
Solution Approach 1:
The patent transitions from traditional 2D trench capacitor structures to a 3D configuration by extending trench segments vertically across multiple device layers. Multiple 2D trench capacitors are stacked in the vertical dimension and connected in parallel, transforming the capacitor architecture from planar to volumetric. This dimensional change increases capacitance density without proportionally increasing footprint area, as the capacitance accumulates through vertical stacking rather than lateral expansion.
Solution Approach 2:
The patent implements nesting by placing multiple trench capacitor structures within each other across different device layers. The trench segments are nested vertically, with each layer's capacitor structure contained within the overall 3D assembly. This nested arrangement allows multiple capacitive elements to occupy overlapping vertical spaces, effectively packing more capacitance into a smaller footprint while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Manufacturing precision
If hybrid bonding is used to connect multiple device layers, then alignment precision can be improved, but void formation occurs and manufacturing complexity increases
Solution Approach 1:
The patent introduces fusion bonding as an intermediary process between traditional hybrid bonding and final device assembly. Fusion bonding serves as a preparatory step that creates preliminary bonds with controlled characteristics, allowing subsequent hybrid bonding to achieve better alignment precision. The fusion bonding process mediates the complexity by creating a intermediate bonding state that is more tolerant to misalignment, thereby reducing void formation and simplifying the overall manufacturing process despite the additional step.
Solution Approach 2:
The patent applies preliminary action by performing fusion bonding before final hybrid bonding to pre-establish connections between device layers. This preliminary bonding action creates a stable foundation that facilitates subsequent precise alignment operations. By performing the fusion bonding step in advance, the patent prepares the interfaces for hybrid bonding in a way that reduces the risk of void formation during final assembly, thereby improving manufacturing precision without proportionally increasing complexity.
3Quantity of substance
If trench depth is increased to enhance capacitance density, then capacitance increases, but manufacturing precision requirements increase and void formation risk increases
Solution Approach 1:
The patent segments the deep trench structure into multiple shallower trench segments distributed across different device layers. Rather than creating one extremely deep trench in a single layer, the capacitor structure is divided into several moderate-depth trenches stacked vertically. Each segment is fabricated within its own layer using standard trench capacitor processes, avoiding the need for ultra-precise deep trench etching in a single step. The segments are then connected through vertical conductive paths, achieving high capacitance through cumulative effect rather than single deep structure.
Data Source
AI summary
Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.