Offset-Stacked Semiconductor Package With Thick Adhesive Support
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reduced size, improved structural characteristics, and enhanced electrical properties while maintaining structural stability and simplifying the fabrication process.
Innovation Solution
A semiconductor package is designed with a package substrate, a first chip stack featuring a first semiconductor chip and offset-stacked second semiconductor chips, and a molding layer. The first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips, and the chips are supported by a thick adhesive layer for enhanced stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor chips are stacked vertically to reduce package size, then the package footprint is reduced, but structural stability deteriorates
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked configuration, placing multiple semiconductor chips at different vertical levels. The offset stacking arrangement distributes chips across multiple height planes, achieving compact footprint while maintaining structural integrity through vertical dimension utilization.
Solution Approach 2:
The patent employs asymmetric offset stacking where chips are positioned at different horizontal offsets rather than perfect vertical alignment. This asymmetric arrangement creates a more stable structural distribution, preventing concentration of stress at single points while maintaining reduced footprint dimensions.
2Quantity of substance
If multiple devices are integrated into a single package to reduce size, then the number of components is reduced, but fabrication complexity increases
Solution Approach 1:
The patent divides the integrated package into distinct chip modules that can be fabricated separately on semiconductor wafers and then stacked. This segmentation allows independent optimization of each chip type while simplifying the overall fabrication process through modular assembly of pre-fabricated units.
Solution Approach 2:
The patent uses a universal adhesive layer design that serves multiple functions: electrical insulation between chips, mechanical bonding support, and structural spacing maintenance. This multi-functional approach simplifies fabrication by eliminating the need for separate components for each function.
3Volume of stationary object
If chips are closely stacked to reduce package volume, then space utilization is improved, but structural stability worsens
Solution Approach 1:
The patent introduces thick adhesive layers as intermediary elements between stacked chips. These adhesive layers provide mechanical support and stress distribution, enabling close stacking for compact volume while maintaining structural stability through the cushioning and bonding function of the adhesive material.
Solution Approach 2:
The patent increases the thickness parameter of adhesive layers beyond conventional thin bonding layers. This parameter change provides sufficient mechanical support and electrical insulation, allowing chips to be stacked at close intervals while maintaining structural integrity and stability.
Data Source
AI summary
A semiconductor package comprises a package substrate and a first chip stack. The first chip stack includes: a first semiconductor chip on the package substrate, a plurality of second semiconductor chips that are on the first semiconductor chip and have an offset stack structure, and a plurality of first adhesive layers that are respectively on a bottom surface of the first semiconductor chip and bottom surfaces of the second semiconductor chips. The first semiconductor chip includes: a first semiconductor substrate, a plurality of first integrated elements on a top surface of the first semiconductor substrate, and a first wiring layer on the top surface of the first semiconductor substrate. A width of the first semiconductor chip and a width of a lowermost one of the second semiconductor chips are the same. The first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips.