Semiconductor Package Stacks with Differential Adhesive Thermal Expansion

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Solution Overview

Problem

The increasing demand for miniaturization and multi-functionality in electronic devices has led to a need for semiconductor packages with vertically stacked semiconductor chips, where existing solutions face challenges in managing thermal expansion and warpage due to differences in chip sizes and surface roughness.

Innovation Solution

A semiconductor package design featuring two stacks of semiconductor chips with different widths, each with its own adhesive layers, where both adhesive layers have the same coefficient of thermal expansion, and a molding member covers the stacks to manage warpage by varying the distribution of adhesive layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor chips of different sizes are vertically stacked to achieve miniaturization and multi-functionality, then the package density and functionality are improved, but thermal expansion differences and warpage occur due to size variations

Engineering Contradiction:
Improvepackage densityVSAvoidstructural stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by using adhesive layers with different coefficients of thermal expansion at different locations. Specifically, the first adhesive layer (between chips of different sizes) has a different thermal expansion coefficient than the second adhesive layer (between chips of similar sizes), allowing each region to compensate for thermal stress locally. This resolves the contradiction by maintaining structural stability while preserving the high-density stacked configuration.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of thermal expansion coefficient in the adhesive layers to address warpage issues. By selecting adhesive materials with appropriate thermal expansion coefficients that match the adjacent semiconductor chips, the patent compensates for thermal stress caused by size variations, thereby maintaining structural stability in the miniaturized stacked package.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If adhesive layers with different coefficients of thermal expansion are used to compensate for size differences, then warpage is reduced, but the manufacturing complexity increases

Engineering Contradiction:
Improvewarpage controlVSAvoidadhesive layer configuration
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent segments the adhesive structure into multiple adhesive layers with different thermal expansion coefficients. The first adhesive layer is positioned between semiconductor chips of different sizes, while the second adhesive layer is positioned between chips of similar sizes. This segmentation allows each layer to be optimized for its specific location, controlling warpage effectively while maintaining a manageable manufacturing process.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces warpage by ensuring greater shrinkage in one portion of the package, preventing smile or crying warpage, and allows for efficient stacking of chips with different sizes, enhancing the package's structural integrity and functionality.

Implementation Method 1

The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11721669B2Semiconductor package including a first semiconductor stack and a second semiconductor stack of different widths
Publication Date: 2023.08.08 SAMSUNG ELECTRONICS CO LTD
  • US11721669B2 patent drawing
  • US11721669B2 patent drawing
  • US11721669B2 patent drawing

AI summary

A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.