Semiconductor Package Affixing Blocks for Thermal Stress Relief
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in integrating multiple semiconductor dies and modules while maintaining structural integrity and reliability, particularly due to thermal stress and warpage issues during manufacturing processes.
Innovation Solution
The use of insulating affixing blocks, formed from polymer materials, is introduced between semiconductor dies and modules to provide stress relief and improve structural stability, utilizing a redistribution circuit structure to connect components and minimize warpage through a combination of elastic modulus and thermal expansion coefficient mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor dies and modules are integrated into a compact package, then the integration density and functionality are improved, but thermal stress and warpage issues worsen during manufacturing processes
Solution Approach 1:
The patent introduces an intermediary layer (underfill material or stress compensation layer) between the semiconductor dies/modules and the substrate. This intermediary layer acts as a buffer to absorb and distribute thermal stress, preventing direct stress transmission that would cause warpage or delamination. The layer mediates the mechanical and thermal interactions between components with different expansion coefficients, thereby maintaining structural integrity while allowing high integration density.
Solution Approach 2:
The patent modifies physical parameters of the package structure, such as adjusting the thickness, material composition, or elastic modulus of intermediate layers to optimize stress distribution. By changing these parameters, the package can accommodate thermal expansion differences without compromising structural integrity, thus resolving the contradiction between high integration and reliability during thermal processes.
2Reliability
If insulating affixing blocks are added to reduce stress and improve reliability, then structural stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the stress relief function into discrete insulating affixing blocks positioned at critical locations rather than using a continuous complex structure. These blocks are strategically placed at corners or edges where stress concentration occurs, providing effective stress relief while minimizing the overall addition to device complexity. The segmented approach allows selective reinforcement only where needed.
Solution Approach 2:
The insulating affixing blocks provide localized stress relief and electrical isolation at specific critical areas of the package. Rather than uniformly increasing complexity across the entire package, the blocks are placed only where stress concentration and electrical isolation are most needed, such as at module corners or between adjacent modules. This local quality approach improves reliability without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insulating affixing blocks enhance the reliability and yield of semiconductor packages by reducing delamination and cracking, ensuring stable attachment of modules during thermal processes and maintaining consistent module thickness.
Implementation Method 1
minimize warpage through a combination of elastic modulus and thermal expansion coefficient mismatch
Implementation Method 2
minimize warpage through a combination of elastic modulus and thermal expansion coefficient mismatch
Implementation Method 3
The first module is disposed on and electrically connected to the redistribution circuit structure by first connectors disposed between the redistribution circuit structure and the first module
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.