Semiconductor Package Air Cavity and Via Design
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Solution Overview
Problem
Conventional multi-chip packaging solutions are costly, complex, and prone to chip damage due to high precision wire bonding and chip embedding methods, which lack flexibility and result in increased manufacturing complexity and yield loss, especially for MEMS sensors where encapsulation materials can interfere with sensitive components.
Innovation Solution
A chip-package design featuring a carrier with stacked chips, where vias extend through the encapsulation to provide electrical and thermal connections, and a cavity is formed between the chip and the carrier, allowing for a gap that can be sealed with a material like polymer clay or glue, and vent holes to relieve pressure during curing, reducing package height and cost while protecting sensitive areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional multi-chip packaging solutions use multiple PCBs to stack chips, then chip integration is achieved, but overall packaging cost increases and manufacturing complexity increases
Solution Approach 1:
The patent merges multiple PCBs into a single carrier board with integrated stacking structures. The carrier includes a first PCB with a first chip and a second PCB with a second chip stacked vertically, connected through conductive vias. This consolidation reduces the number of separate packaging components and simplifies the manufacturing process while maintaining multi-chip integration capability.
Solution Approach 2:
The patent implements a nested structure where the second PCB is positioned on top of the first PCB, and the second chip is mounted on the second PCB. The conductive vias extend through both PCBs to establish electrical connections between chips at different levels. This nested arrangement achieves multi-chip integration within a compact vertical structure, reducing overall packaging complexity.
2Reliability
If high precision wire bond technique is used for chip stacking, then electrical connection is achieved, but packaging cost increases
Solution Approach 1:
The patent extracts the wire bonding process from the packaging structure and replaces it with direct conductive via connections through the PCBs. The electrical connections are established through conductive material filled vias that penetrate the PCB layers, eliminating the need for separate wire bonding operations and reducing packaging cost while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent introduces conductive vias as intermediaries to establish electrical connections between stacked chips. Instead of using wire bonds that require precise manual or automated bonding operations, the conductive vias provide direct electrical pathways through the PCB structure, simplifying the connection process and reducing cost while ensuring reliable electrical contact.
3Stability of the object's composition
If chip embedding is used, then chip fixation is achieved, but manufacturing complexity increases and flexibility in chip variation is lost
Solution Approach 1:
The patent segments the packaging structure into separate modular units: a carrier board, stacked PCBs, and individually mounted chips. This segmentation allows chips to be mounted on top of the PCB structure rather than embedded within it, enabling easy replacement and variation of different chip types while maintaining stable fixation through standard chip mounting techniques and encapsulation.
4Object-affected harmful factors
If MEMS sensor is covered with metal lid, then protection is achieved, but package height increases
Solution Approach 1:
The patent replaces the traditional metal lid with a thin film encapsulation material that conforms to the MEMS sensor structure. This thin film provides the necessary protection for the MEMS sensor while occupying minimal vertical space, thereby maintaining a compact package height. The encapsulation material forms a protective barrier without the bulk associated with metal lids.
5Object-affected harmful factors
If Si lid is attached by silicone to cover MEMS sensor, then protection is achieved, but package cost increases
Solution Approach 1:
The patent merges the protective cover function with the encapsulation material that already surrounds the chips and PCB structure. Instead of adding a separate Si lid with silicone attachment, the encapsulation material is extended to provide protection for the MEMS sensor, consolidating multiple functions into a single structural element and reducing package cost.
6Object-affected harmful factors
If silicone glue is used to cover MEMS sensor, then protection is achieved, but bleeding is hard to control
Solution Approach 1:
The patent extracts the silicone glue from the protective cover application and replaces it with a controlled encapsulation material deposition process. The encapsulation material is applied in a controlled manner to form a precise protective layer over the MEMS sensor, eliminating the uncontrolled bleeding issue associated with silicone glue while maintaining effective protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces manufacturing complexity, minimizes chip damage, and offers flexibility in chip variation, while ensuring the sensitive areas of MEMS sensors are protected from encapsulation materials, leading to a more efficient and cost-effective packaging solution with improved yield and reduced package size.
Implementation Method 1
an electrically conductive material at least partly filling the via to electrically connect the first chip to the second chip
Implementation Method 2
the other plated half of the via may provide a thermal conduction path to the other side of the carrier
Data Source
AI summary
Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.