Semiconductor Package Air-Gap Via Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high electrical properties and structural stability, particularly in the integration of image sensor, logic, and memory chips, due to material and thermal expansion mismatches, which affect electrical insulation and capacitance.
Innovation Solution
A semiconductor package design featuring a spacer structure with a liner layer, capping layer, and air gap between the through via and the semiconductor substrate, providing electrical insulation with a dielectric constant of 1 and acting as a stress buffer to prevent direct contact and distortion, thereby enhancing electrical properties and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through via is used to electrically connect wiring layers through the semiconductor substrate, then electrical connectivity is achieved, but parasitic capacitance and tunneling effects increase due to direct contact between the through via and substrate
Solution Approach 1:
The patent introduces an air gap as an intermediary between the through via and the semiconductor substrate. This air gap acts as a mediator that electrically isolates the through via from the substrate, eliminating parasitic capacitance and tunneling effects while still allowing the through via to provide electrical connectivity between wiring layers. The air gap functions as a dielectric barrier that prevents direct electrical interaction between conductive elements.
Solution Approach 2:
The patent extracts the harmful direct contact interface between the through via and the semiconductor substrate by removing the substrate material in the region where the through via would otherwise contact it. This extraction of the substrate material creates the air gap, effectively taking out the source of parasitic capacitance and tunneling effects while preserving the essential electrical connectivity function of the through via.
2Adaptability or versatility
If multiple semiconductor chips are integrated in a stacked configuration, then device functionality and capacity are enhanced, but structural stability deteriorates due to material and thermal expansion mismatches
Solution Approach 1:
The patent applies beforehand cushioning by introducing compliant layers and air gaps between the through via and the semiconductor substrate before thermal and mechanical stresses can cause damage. These air gaps act as pre-positioned cushioning elements that absorb expansion mismatches and thermal stresses, preventing direct transmission of harmful forces between stacked chips and maintaining structural integrity throughout the device lifecycle.
3Volume of moving object
If the through via is positioned close to the semiconductor substrate, then device compactness is improved, but material distortion and stress increase due to thermal expansion mismatches
Solution Approach 1:
The patent employs composite material structures by combining different materials with complementary properties: the through via (conductive material), the air gap (void/dielectric), and the surrounding dielectric layers. This composite structure allows the air gap to serve multiple functions - maintaining electrical isolation while providing mechanical compliance to accommodate thermal expansion differences between materials, thus reducing stress and preventing distortion in the compact stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical properties by reducing parasitic capacitance and tunneling effects, while increasing structural stability by preventing material distortion and stress, resulting in a more reliable semiconductor package.
Implementation Method 1
providing electrical insulation with a dielectric constant of 1
Implementation Method 2
acting as a stress buffer to prevent direct contact and distortion
Data Source
AI summary
A semiconductor package includes first, second, and third semiconductor chips. The second semiconductor chip includes a semiconductor substrate, a first wiring layer on a first surface of the semiconductor substrate, a second wiring layer on a second surface of the semiconductor substrate, and a through via that penetrates the semiconductor substrate and electrically connects the first wiring layer and the second wiring layer. The semiconductor substrate and the through via are spaced apart from each other across a spacer structure. The spacer structure includes a first liner layer in contact with the semiconductor substrate, a second liner layer in contact with the through via, an air gap between the first liner layer and the second liner layer, and a capping layer that seals the air gap on the first liner layer and the second liner layer.