Semiconductor Package Alignment Key Structure for Precise Assembly
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high accuracy and reliability due to limitations in alignment and electrical connectivity.
Innovation Solution
The semiconductor package incorporates a first alignment key with a key body extending into the redistribution substrate and a key protrusion, along with a solder via electrically connected to a solder pad, utilizing a non-photosensitive insulating layer with filler grains for improved structural integrity and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photo processes and grinding processes are used for alignment key formation, then manufacturing precision can be improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent extracts and eliminates the photo process and grinding process from the manufacturing sequence by using a non-photosensitive insulating layer that allows direct formation of alignment keys through simple patterning and etching processes, thereby reducing device complexity while maintaining alignment precision
Solution Approach 2:
The non-photosensitive insulating layer is prepared in advance with appropriate material properties (etch selectivity, mechanical strength) that enable direct alignment key formation without requiring subsequent photo lithography or grinding steps, achieving both precision and process simplification
2Manufacturing precision
If photo processes are used for alignment key formation, then manufacturing precision is improved, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent removes the time-consuming photo process from the manufacturing sequence by utilizing a non-photosensitive insulating layer that enables direct alignment key formation through simpler, faster patterning and etching processes, thereby improving productivity while maintaining precision
Solution Approach 2:
The invention skips the intermediate photo lithography step by using material properties of the non-photosensitive insulating layer that allow direct etching of alignment keys, rushing through the manufacturing process more efficiently without sacrificing alignment accuracy
3Manufacturing precision
If grinding processes are used for alignment key formation, then manufacturing precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent extracts and eliminates the grinding process from the manufacturing sequence by using a non-photosensitive insulating layer with appropriate mechanical and etching properties that enable direct alignment key formation, thereby reducing manufacturing cycle time while maintaining alignment precision
Solution Approach 2:
The non-photosensitive insulating layer is pre-configured with material properties that enable direct etching of alignment keys without requiring subsequent grinding operations, achieving both time efficiency and precision
Data Source
AI summary
Provided is a semiconductor package including a first redistribution substrate including a first redistribution insulating layer and a first redistribution via, a first insulating layer on the first redistribution substrate, a solder pad on the first insulating layer, a first alignment key penetrating the first insulating layer and extending to an inside of the first redistribution insulating layer, and a solder via spaced apart from the first alignment key and electrically connected to the solder pad, wherein the first alignment key includes a first key body extending from a first surface of the first insulating layer to the inside of the first redistribution substrate, and a first key protrusion protruding from a side surface of the first key body toward the first insulating layer, and wherein the first insulating layer includes a non-photosensitive material.