Semiconductor Package Antenna Integration via RDL
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging integrated circuits with high-speed and high-density requirements, as existing packaging methods struggle to efficiently integrate antennas and reduce package height and cost while maintaining flexibility and robustness.
Innovation Solution
The integration of a conformally coated antenna within the packaging process, utilizing a redistribution layer (RDL) for horizontal connections and through-vias for vertical connections, which reduces package height and cost, and allows for flexible antenna design, with the antenna being grounded through the RDL and through-vias for efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging methods are used for high-speed and high-density integrated circuits, then electrical connectivity and signal transmission are maintained, but package height and cost increase while flexibility is reduced
Solution Approach 1:
The patent combines the antenna structure with the packaging substrate by forming conductive traces directly on the substrate surface, merging two previously separate components (antenna and package) into a single integrated structure. This eliminates the need for separate antenna mounting and reduces overall package height while maintaining electrical connectivity for both IC signals and antenna functions.
Solution Approach 2:
The patent transitions from vertical stacking (increasing package height) to planar integration on the substrate surface. By utilizing the two-dimensional surface area of the packaging substrate for antenna trace formation, the design achieves high-density integration without increasing the vertical dimension, thus reducing package height while maintaining all necessary electrical connections.
2Reliability
If traditional packaging methods are used for high-speed and high-density integrated circuits, then electrical connectivity and signal transmission are maintained, but package cost increases while flexibility is reduced
Solution Approach 1:
The patent merges the antenna fabrication process with the existing packaging process by forming conductive traces on the packaging substrate using standard PCB or thin-film deposition techniques. This consolidation eliminates separate antenna manufacturing and assembly steps, reducing labor, materials, and process complexity, thereby lowering overall package cost while maintaining reliable electrical connectivity.
Solution Approach 2:
The packaging substrate serves dual functions: it provides mechanical support for the IC and simultaneously acts as the antenna structure through its integrated conductive traces. This self-service approach eliminates the need for separate antenna components and assembly operations, reducing manufacturing complexity and cost while ensuring reliable electrical connections for both IC I/O and antenna functions.
3Strength
If traditional packaging methods are used for high-speed and high-density integrated circuits, then robustness is maintained, but integration density and area utilization decrease
Solution Approach 1:
The patent utilizes the two-dimensional surface area of the packaging substrate for integrating antenna traces and IC I/O connections, rather than consuming additional vertical space. This planar integration approach maximizes area utilization by arranging conductive elements in the XY-plane on the substrate surface, achieving high integration density without compromising the mechanical robustness of the package structure.
Solution Approach 2:
The packaging substrate is designed to perform multiple functions simultaneously: mechanical support for the IC, electrical interconnection for IC I/O pins, and antenna radiation element. This multi-functionality allows the same substrate area to serve both structural and electromagnetic purposes, increasing effective integration density without requiring additional package area or sacrificing robustness.
Data Source
AI summary
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.