Semiconductor Package Antenna Trench Integration
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-performance, compact designs with reduced size and minimized interference between components, particularly for mm-wave and 5G communication devices, while maintaining low failure rates and simplifying the fabrication process.
Innovation Solution
A semiconductor package design featuring a package substrate with a semiconductor chip, a mold layer, an antenna pattern, and connection terminals that fill trenches in the mold layer, allowing for electrical connection between the antenna pattern and the substrate, along with a dielectric layer to reduce parasitic capacitance, enabling compact size and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the antenna module size is reduced for compact design, then the size parameter is improved, but component interference increases and design flexibility deteriorates
Solution Approach 1:
The patent transitions the antenna structure from a planar two-dimensional layout to a three-dimensional configuration by forming trenches in the mold layer and placing connection terminals within these trenches. This vertical dimensionality change allows the antenna pattern to be electrically connected to the substrate through the trench-filled terminals, reducing the horizontal footprint and enabling compact module design while maintaining electrical performance and reducing component interference.
2Volume of moving object
If multiple components are mounted in a single package to reduce size, then the package volume is reduced, but the fabrication process complexity increases
Solution Approach 1:
The patent merges the antenna structure formation with the existing mold layer fabrication process. The trenches are formed in the mold layer using the same photolithography and etching processes already employed for other package features. Connection terminals are then filled into these trenches and the antenna pattern is formed, integrating multiple functions into a unified fabrication sequence that reduces overall process complexity despite the three-dimensional structure.
3Reliability
If the antenna is electrically connected through the mold layer, then the electrical characteristics are improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent forms the trenches in the mold layer before depositing the connection terminals and antenna pattern. This preliminary action allows the trench geometry and position to be established with high precision using photolithography masks, ensuring accurate alignment. The subsequent filling process then follows the pre-defined trench pathways, maintaining manufacturing precision while achieving reliable electrical connection between the antenna and substrate.
Data Source
AI summary
A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a mold layer on the package substrate to cover the semiconductor chip, the mold layer having a first side surface and a first trench disposed at the first side surface, and the first trench extending from a top surface of the mold layer toward a bottom surface of the mold layer, an antenna pattern on the mold layer, and a first connection terminal filling the first trench. The antenna pattern is electrically connected to the package substrate through the first connection terminal.