Semiconductor Package Anti-Contact Layer Design
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Solution Overview
Problem
As semiconductor devices become thinner, smaller, and lighter, the miniaturization process leads to signal delays due to increased interconnection lines, and existing techniques for stacking semiconductor chips, such as the through silicon via (TSV) method, face limitations in enhancing chip performance.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip, a second semiconductor chip stacked on the first, with connection members featuring a connection pad, a bonding member, and an anti-contact layer to prevent the bonding member from extending along the side surfaces of the connection pad, thereby reducing tensile forces and improving reliability and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the bonding member is allowed to extend along the side surfaces of the connection pad to ensure adequate bonding area, then bonding strength is improved, but tensile stress on the semiconductor chip increases and reliability deteriorates
Solution Approach 1:
The patent introduces an anti-contact layer as an intermediary substance between the bonding member and the connection pad. This layer has controlled wettability that prevents the bonding member from extending along the side surfaces of the connection pad, thereby eliminating the source of tensile stress while maintaining adequate bonding area on the upper surface. The anti-contact layer acts as a mediator that allows bonding to occur only in the desired region.
Solution Approach 2:
The patent applies different surface properties to different regions of the connection pad. The upper surface of the connection pad maintains high wettability to ensure adequate bonding between the bonding member and the pad, while the side surfaces are covered with an anti-contact layer that has low wettability. This local differentiation of surface properties allows the bonding member to bond effectively to the pad without extending along the sides, thus preventing tensile stress generation.
2Reliability
If the connection pad area is increased to improve electrical connectivity and bonding area, then electrical performance is improved, but the device footprint increases contradicting miniaturization goals
Solution Approach 1:
The patent addresses the footprint issue by optimizing the vertical arrangement and bonding interface efficiency rather than simply increasing the horizontal area of the connection pad. By controlling the bonding member geometry and using the anti-contact layer to prevent lateral extension, the design achieves adequate bonding strength and electrical connectivity through optimized interface quality rather than increased area, thus maintaining miniaturization.
3Reliability
If the bonding member geometry is optimized to reduce tensile forces, then reliability is improved, but bonding area may be reduced affecting bonding strength
Solution Approach 1:
The anti-contact layer serves as a mediator that decouples the relationship between bonding member geometry and tensile stress generation. By preventing the bonding member from contacting the insulating layer along the side surfaces, the anti-contact layer allows for optimized bonding member geometry that minimizes tensile forces without sacrificing bonding area on the upper surface, thus simultaneously improving reliability and maintaining bonding strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces tensile stress on the semiconductor package, enhancing its reliability and durability by preventing the bonding member from contacting the insulating layer, thus maintaining electrical connectivity while preventing unwanted bonding.
Implementation Method 1
The bonding member may have low wettability on the anti-contact layer than on the connection pad
Implementation Method 2
The design effectively reduces tensile stress on the semiconductor package, enhancing its reliability and durability by preventing the bonding member from contacting the insulating layer
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.