Semiconductor Package Asymmetric Chip Orientation Suppresses Warpage
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Solution Overview
Problem
Semiconductor packages face issues of twist or warpage due to their decreasing size and asymmetric structures, which can lead to structural instability and failures.
Innovation Solution
The semiconductor package design includes multiple semiconductor chips with specific orientations on a substrate, where the long sides of the chips are parallel or perpendicular to the diagonal lines of the substrate, creating a binding force that suppresses twist or warpage by ensuring all sides are not parallel to the substrate sides, and the chips are stacked with overlapping configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor package size is reduced and the molding part is made thinner, then the package meets consumer demands for smaller electronic devices, but twist or warpage occurs in the semiconductor package
Solution Approach 1:
The patent applies asymmetry by configuring semiconductor chips with different orientations - the first chip has its long side parallel to the substrate's long side, while the second chip has its long side perpendicular to the substrate's long side. This asymmetric arrangement creates balanced binding forces that counteract each other, suppressing twist and warpage in the thinned semiconductor package structure.
2Length of moving object
If an asymmetric structure is used in the semiconductor package, then the package can be made thinner, but twist or warpage occurs due to the asymmetric configuration
Solution Approach 1:
The patent deliberately introduces asymmetry in chip orientations to enable thinned package design while maintaining stability. The first semiconductor chip is oriented with its long side parallel to the substrate's long side, and the second chip is oriented with its long side perpendicular to the substrate's long side, creating counterbalancing forces that prevent warpage in the asymmetric, thinned structure.
Solution Approach 2:
The patent uses counterbalancing forces by positioning and orienting multiple semiconductor chips such that their binding forces act in opposite directions. The first chip provides binding force in one orientation while the second chip provides binding force in a perpendicular orientation, creating a counterweight effect that suppresses twist and warpage in the thinned package.
3Stability of the object's composition
If multiple semiconductor chips are stacked with specific orientations, then twist or warpage is suppressed, but the device complexity increases
Solution Approach 1:
The patent manages device complexity by implementing a systematic asymmetric configuration rather than random arrangement. The first chip is oriented parallel to the substrate's long side and the second chip is oriented perpendicular to it, providing a clear, repeatable pattern that suppresses warpage while maintaining manufacturability and assembly feasibility.
Data Source
AI summary
Provided is a semiconductor package including a substrate, a first semiconductor chip disposed on the substrate to have a rectangular shape with long and short sides, and a second semiconductor chip disposed on the first semiconductor chip to have a rectangular shape with long and short sides. Centers of the first and second semiconductor chips may be located at substantially the same position as that of the substrate, and the long side of the first semiconductor chip may be substantially parallel to a diagonal line of the substrate. Further, the long side of the second semiconductor chip may be not parallel to that of the first semiconductor chip.