Semiconductor Package Substrate With Back-Surface Plating Wires
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Solution Overview
Problem
Semiconductor packages face issues with increased hygroscopic properties and potential failures like cracks and explosions due to the exposure of lead-in wires for electrolytic gold plating, especially when mixed with resin additives that affect transparency, and the cumbersome nature of electroless plating processes.
Innovation Solution
The solution involves forming electrolytic metal films on both surfaces of a substrate with passages for electrical connection, where lead-in wires for electrolytic plating are only on the back surface, preventing exposure to resin and using an electrolytic plating process to ensure strong wire bonding without additives, and incorporating image processing to verify proper plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If lead-in wires for electrolytic gold plating are formed on the mounting surface and connected to electrode patterns, then electrolytic plating can be performed to strengthen wire bonding, but the lead-in wires become exposed at edge surfaces after dicing, increasing hygroscopic properties and causing package failures
Solution Approach 1:
The lead-in wires for electrolytic plating are extracted from the mounting surface and relocated exclusively to the back surface of the substrate. This separation removes the source of the problem (exposed lead-in wires) from the sealed package structure, preventing moisture ingress while preserving the electrolytic plating function on the back surface electrode patterns that will be soldered to the circuit board
Solution Approach 2:
The lead-in wires are moved from the two-dimensional plane of the mounting surface to the back surface, utilizing the third dimension (substrate thickness) to resolve the conflict. By placing lead-in wires only on the back surface, the patent creates a spatial separation between the plating function and the sealed package structure
2Strength
If electrolytic gold plating is performed to strengthen wire bonding, then wire bonding strength is improved, but the plating process becomes cumbersome and requires precise control
Solution Approach 1:
The lead-in wires for electrolytic plating are formed on the back surface before the semiconductor chips are mounted and before the resin sealing is applied. This preliminary positioning ensures that the plating function is established without requiring complex in-situ plating structures, simplifying the overall manufacturing process
3Reliability
If resin additives are used to control hygroscopic properties, then moisture absorption is reduced, but the resin transparency is affected
Solution Approach 1:
The patent removes the need for hygroscopicity-controlling additives from the resin by extracting the source of moisture problems (exposed lead-in wires) through structural design. The lead-in wires are confined to the back surface, eliminating the need for chemical additives and preserving resin transparency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the hygroscopic properties and failure rates of semiconductor packages, maintains wire bonding strength, and allows for transparent resin sealing, enhancing the reliability and efficiency of the semiconductor package production process.
Implementation Method 1
an electrolytic plating process necessary for obtaining enough strength for wire bonding
Data Source
AI summary
A semiconductor package for surface mounting has a substrate having electrode patterns formed on both its surfaces which are electrically connected through passages such as throughholes formed through the substrate, all of these electrode patterns having a metal film formed by an electrolytic plating process. Semiconductor chips are wire-bonded onto one its surfaces (mounting surface) which is sealed with a resin layer. Lead-in wires each with one end exposed externally are included only those of the electrode patterns on the back surface of the substrate opposite its mounting surface such that the mounting surface has no lead-in wires with a part exposed externally.