Fan-Out Semiconductor Package With Exposed Backside Heat Spreading

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in improving thermal and electrical performance while maintaining process efficiency, particularly in flip chip type packaging, which is limited by individual chip processing and lacks effective heat dissipation and electrical connection methods.

Innovation Solution

A semiconductor package device incorporating a redistribution layer member, a molding layer that exposes the chip backside, a thermal interface material member, and a heat spreading member, with conductive contact elements and through-holes for thermal and electrical connections, forming a fan-out package structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing flip chip type packaging is performed by mounting individual chips on package substrates, then each chip can be packaged, but process efficiency is greatly reduced and thermal/electrical performance improvement is limited

Engineering Contradiction:
Improveprocess efficiencyVSAvoidpackaging structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple individual chip packaging processes into a single integrated fan-out package structure. Multiple chips are mounted on a package substrate and collectively enclosed by a single molding layer, with a common heat dissipation cover covering all chips. This consolidation eliminates repetitive individual packaging steps and enables batch-level processing, dramatically improving productivity while reducing overall structural complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The package substrate serves multiple functions simultaneously: it provides mechanical support for mounting multiple chips, enables electrical connections through redistribution layers, facilitates thermal management through integrated heat dissipation structures, and allows for unified encapsulation by the molding layer. This multi-functionality resolves the contradiction by enabling efficient packaging of multiple chips without proportionally increasing structural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Temperature

If adhesive is used to attach heat dissipation cover to package substrate and chip, then thermal connection is established, but thermal performance and electrical performance cannot be effectively improved

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidthermal/electrical performance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces a thermal interface material as an intermediary layer between the heat dissipation cover and the chips/package substrate. This specialized material provides superior thermal conductivity compared to standard adhesives, enabling more effective heat transfer from the chips through the package substrate to the heat dissipation cover. The thermal interface material specifically addresses thermal performance without compromising electrical isolation, thereby resolving the contradiction between heat dissipation and overall device reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The heat dissipation cover is constructed using composite materials that combine high thermal conductivity with appropriate mechanical and electrical properties. This composite structure enables effective thermal management while maintaining electrical isolation and mechanical stability, simultaneously improving both thermal performance and device reliability without relying solely on adhesive bonding.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If molding layer covers the chip completely, then chip is protected, but backside of chip cannot be accessed for thermal interface material application

Engineering Contradiction:
Improvechip protectionVSAvoidthermal interface material application
Core Design Contradiction:
Ease of manufactureVSEase of operation

Solution Approach 1:

The patent applies the thermal interface material to the package substrate or heat dissipation cover before the molding layer is fully formed or cured. This preliminary application ensures that the thermal interface material is in place for optimal thermal contact before the chip becomes completely encapsulated. The molding layer is then applied to provide complete protection, while the pre-applied thermal interface material remains accessible and functional, resolving the contradiction between protection and manufacturability.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances thermal and electrical performance while increasing manufacturing efficiency by improving heat dissipation and electrical connections through a fan-out package design.

Implementation Method 1

a thermal interface material member disposed on the molding layer in contact with the backside of the at least one chip

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a heat spreading member disposed on the thermal interface material member

Methodology Applied
Scientific EffectHeat spreading: Conduction (thermal)

Data Source

PatentUS20250309038A1Semiconductor package device and method of manufacturing the same
Publication Date: 2025.10.02 SILICON BOX PTE LTD
  • US20250309038A1 patent drawing
  • US20250309038A1 patent drawing
  • US20250309038A1 patent drawing

AI summary

Disclosed are a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes a redistribution layer member, at least one chip disposed on a first surface of the redistribution layer member, the at least one chip being electrically connected to the redistribution layer member, a molding layer disposed on the first surface of the redistribution layer member so as to at least partially expose a backside of the at least one chip while filling a space around the at least one chip, a thermal interface material member disposed on the molding layer in contact with the backside of the at least one chip, and a heat spreading member disposed on the thermal interface material member.