Semiconductor Package Backside Wiring for Batch Power and Heat Routing

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in improving process efficiency while ensuring electrical and thermal performance, particularly in handling materials for power, ground, and heat dissipation, and are limited by individual chip processing.

Innovation Solution

A semiconductor package device with a redistribution layer member, electrical contact elements, and connection wiring members that expose the backside of chips through through-holes, allowing for improved electrical and thermal performance and manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing packaging processes are used for each individual chip, then electrical connection and heat dissipation requirements can be met, but process efficiency is greatly reduced

Engineering Contradiction:

Improveprocess efficiencyVSAvoidhandling and processing of various materials

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple individual chip packaging processes into a single batch processing operation. Multiple chips are mounted simultaneously on a lead frame, and electrical connections are established for all chips in one wire bonding or clip bonding operation, rather than processing each chip separately. This combining of operations dramatically improves productivity while reducing the overall complexity of material handling.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The lead frame structure serves multiple functions simultaneously: it provides mechanical support for multiple chips, establishes electrical connections for power and ground, and facilitates heat dissipation. This multi-functional design eliminates the need for separate components for each function, streamlining the packaging process and improving efficiency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If backside power delivery network (BSPDN) structure is used, then power supply efficiency is improved, but manufacturing technology is still lacking for improving process efficiency while ensuring electrical connection and heat dissipation performance

Engineering Contradiction:

Improvepower supply efficiencyVSAvoidmanufacturing process efficiency

Core Design Contradiction:

Use of energy by moving objectVSEase of manufacture

Solution Approach 1:

The patent implements preliminary actions by pre-forming power and ground pads on the backside of the semiconductor chip before chip mounting. The BSPDN structure is prepared in advance with power supply lines extending to the backside, and connection structures are pre-formed on the lead frame. This preliminary preparation enables efficient batch processing and simplifies subsequent packaging operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent transitions from traditional frontside power delivery to backside power delivery, utilizing the third dimension (chip thickness direction) to improve power supply efficiency. By delivering power through the backside of the chip, the BSPDN reduces current path length and resistance, improving power efficiency while enabling new manufacturing approaches.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional packaging methods are used, then individual chip requirements can be met, but material costs and process time increase

Engineering Contradiction:

Improveelectrical connection performanceVSAvoidprocess time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Multiple chips are processed simultaneously in batch operations rather than individually. Wire bonding or clip bonding is performed for multiple chips in one operation, and molding is applied to the entire array at once. This merging of operations maintains reliable electrical connections for each chip while dramatically reducing total process time.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If conventional packaging methods are used, then individual chip requirements can be met, but material costs increase

Engineering Contradiction:

Improveheat dissipation functionVSAvoidmaterial costs

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The lead frame and molding compound serve multiple functions: mechanical support, electrical connection, and heat dissipation. The heat dissipation function is integrated into the existing packaging structure rather than requiring separate heat sinking components for each chip. This multi-functionality reduces material costs while maintaining reliable thermal performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250309173A1Semiconductor package device and method of manufacturing the same

Publication Date: 2025.10.02 SILICON BOX PTE LTD

AI summary

Disclosed are a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes a redistribution layer member having at least one electrical contact element around an active region, at least one chip disposed on a first surface of the redistribution layer member, the chip being electrically connected to the redistribution layer member, a molding layer disposed on the first surface of the redistribution layer member so as to expose a backside of the chip while filling a space around the chip, the molding layer having at least one through-hole configured to expose the electrical contact element, and a connection wiring member disposed on the molding layer, the connection wiring member being configured to be electrically connected to the electrical contact element through the through-hole and to be electrically connected to the backside of the chip.