Semiconductor Package Structure With Balance Layer Against Warpage
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Solution Overview
Problem
The increasing integration of electronic components in semiconductor chips leads to reliability issues such as warpage during manufacturing and in the final product, due to uneven wiring densities and thermal expansion coefficient differences between components.
Innovation Solution
A semiconductor package structure is designed with a substrate, semiconductor device, encapsulant, balance structure, and warpage-resistant layer, where the balance structure and warpage-resistant layer are strategically positioned to compensate for warpage caused by substrate stress and thermal expansion differences, and the encapsulant forms a 'moldlock' structure for enhanced adhesion and structural strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of electronic components is increased to achieve improved electrical performance and additional functions, then the functionality and electrical performance are improved, but warpage occurs more easily during manufacturing and in the final product
Solution Approach 1:
The patent applies local quality by introducing a balance structure with specific material properties (different thermal expansion coefficient) at a localized position (back surface of semiconductor device) to counteract the warpage caused by uneven wiring densities on the front surface. This localized structural modification addresses the warpage issue without changing the overall device functionality.
Solution Approach 2:
The patent employs asymmetry by creating an asymmetric structure where the balance structure is added only on the back surface of the semiconductor device, while the front surface maintains its original configuration with electronic components and wiring. This asymmetric design allows the back surface to compensate for the warpage induced by the asymmetric wiring density distribution on the front surface.
2Adaptability or versatility
If more electronic components are integrated, then additional functions are achieved, but thermal expansion coefficient differences between components increase, leading to warpage
Solution Approach 1:
The patent applies parameter changes by modifying the thermal expansion coefficient parameter of the balance structure material to be different from that of the semiconductor device. This parameter mismatch is intentionally designed to create a compensatory effect that counteracts the warpage caused by thermal expansion coefficient differences among the various electronic components integrated on the device.
3Adaptability or versatility
If uneven wiring densities are present on the semiconductor chip, then specific functional requirements are met, but stress concentration occurs leading to warpage
Solution Approach 1:
The patent implements the counterweight principle by introducing the balance structure on the back surface of the semiconductor device to act as a counterbalancing element. This balance structure generates opposing stress that counteracts the stress concentration caused by uneven wiring densities on the front surface, thereby preventing warpage while maintaining the required functional wiring configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents warpage and improves the reliability of semiconductor packages by compensating for stress and thermal expansion differences, while enhancing adhesion and structural strength through symmetric arrangement and heat dissipation.
Implementation Method 1
warpage may easily occur during the manufacturing process as well as to the final product due to uneven wiring densities and thermal expansion coefficient differences between components
Implementation Method 2
the encapsulant is engaged with the substrate and the balance structure to form a 'moldlock' structure
Data Source
AI summary
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.