Semiconductor Package Wiring Layout for Balanced Control Capacitance
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving stable characteristics and efficient loss reduction due to non-uniform wiring lengths and parasitic capacitance between control electrodes, leading to operational instability and reliability issues.
Innovation Solution
A semiconductor package design with a specific arrangement of wiring layers and connection members that overlap in a defined direction, ensuring uniform wiring lengths and balanced parasitic capacitance, along with elastic connection members for stable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wiring layers are arranged in a conventional manner, then device complexity is reduced, but manufacturing precision deteriorates due to non-uniform wiring lengths and unbalanced parasitic capacitance
Solution Approach 1:
The patent transitions from planar wiring arrangement to a three-dimensional stacked configuration where first, second, and third wiring layers are positioned at different heights along the thickness direction. This dimensional change enables uniform wiring lengths to be achieved while maintaining manageable device complexity through systematic layering.
Solution Approach 2:
The wiring structure is divided into multiple independent wiring layers (first, second, and third wiring layers) that can be separately configured and optimized. Each layer serves specific connection functions, allowing precise control over wiring lengths and parasitic capacitance distribution without overwhelming complexity.
2Reliability
If conventional wiring arrangement is used, then ease of manufacture is improved, but reliability deteriorates due to operational instability from non-uniform wiring lengths
Solution Approach 1:
Different wiring layers are assigned specific local functions: the first wiring layer connects to the first control electrode, the second wiring layer to the second control electrode, and the third wiring layer to the first conductive member. This localized functional assignment ensures uniform electrical characteristics and stable operation while maintaining manufacturability through standardized connection patterns.
3Loss of energy
If wiring layers are positioned to achieve uniform lengths, then loss reduction is improved, but device complexity increases due to multi-layer stacking configuration
Solution Approach 1:
Multiple wiring functions are merged into a compact multi-layer structure where first, second, and third wiring layers are stacked in the thickness direction. This consolidation achieves uniform wiring lengths and reduced energy loss while containing the increased complexity within a small vertical footprint, effectively managing the complexity-benefit trade-off.
Data Source
AI summary
According to one embodiment, a semiconductor package includes a first conductive member, a second conductive member, a plurality of semiconductor devices, a wiring member, a first connection member, and a second connection member. The plurality of semiconductor devices is provided between the first conductive member and the second conductive member. One of the semiconductor devices includes a semiconductor member, a first electrode, a first control electrode, a second control electrode, and a second electrode. The first and second conductive members are electrically connected to the first and second electrodes, respectively. The wiring member includes first, second and third wiring layers, and an insulating region. A part of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The second wiring layer includes a first connection region and a second connection region.