Symmetrical Power Semiconductor Package for Balanced Switching
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Solution Overview
Problem
Conventional molded power semiconductor package designs for high-power applications suffer from asymmetrical gate contact connections between high-side and low-side switching nodes, leading to different switching speeds and potential oscillations that can damage the modules.
Innovation Solution
The design incorporates a molded power semiconductor package with a connection frame that provides symmetrical power and gate connections to power semiconductor dies, using structured metal frames and a mold compound to encase the dies and carriers, thereby reducing stray inductance and achieving balanced switching speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional molded power semiconductor package designs are used with asymmetrical gate contact connections, then the package structure is simple and easy to manufacture, but the switching speeds of high-side and low-side differ leading to oscillations and reduced reliability
Solution Approach 1:
The patent applies asymmetry in reverse - it intentionally creates symmetry where previously asymmetry existed. The gate contact connections are redesigned to be symmetrical for both high-side and low-side switches, ensuring equal switching speeds and eliminating oscillations. This symmetry principle resolves the technical contradiction by making the previously asymmetrical gate connections equal, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent implements equipotentiality by ensuring that the gate contact connections have equal electrical characteristics for both high-side and low-side switches. The symmetrical design ensures that both switches experience the same inductance and resistance values, creating equivalent electrical conditions that enable balanced switching speeds and prevent oscillations
2Reliability
If asymmetrical gate contact connections are used, then manufacturing is simpler, but different switching speeds cause oscillations at increased frequencies that can destroy the modules
Solution Approach 1:
The patent applies asymmetry in reverse - it intentionally creates symmetry where previously asymmetry existed. The gate contact connections are redesigned to be symmetrical for both high-side and low-side switches, ensuring equal switching speeds and eliminating oscillations. This symmetry principle resolves the technical contradiction by making the previously asymmetrical gate connections equal, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent changes the electrical parameters of the gate contact connections to achieve symmetry. By adjusting the layout, dimensions, and material properties of the gate contacts, the inductance and resistance values are made equal for both high-side and low-side switches. This parameter optimization enables balanced switching performance while maintaining manufacturability
3Reliability
If derating is applied to prevent oscillations, then module reliability improves, but the power handling capability and performance are reduced
Solution Approach 1:
The patent applies preliminary action by addressing the root cause of oscillations through symmetrical gate contact design before oscillations can occur. By ensuring equal switching speeds through symmetrical connections, the design prevents oscillations from happening in the first place, eliminating the need for derating and maintaining full power handling capability
Data Source
AI summary
A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.