Semiconductor Package Base Frame Segmentation for CTE Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor packaging is reducing stress caused by the mismatch in thermal expansion coefficients between different materials used in the packaging process, which leads to reliability issues and potential damage to the integrated circuit die, especially with the introduction of ultra-low K dielectrics and fine pitch wiring.
Innovation Solution
A semiconductor package design featuring an interposer substrate with a base frame comprising two pieces of materials with different thermal expansion coefficients, connected by deformable structures that absorb differential thermal expansion, allowing for the segregation of thermal expansion between the integrated circuit die and the printed wiring board, thereby reducing stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-material substrate is used to connect the integrated circuit die to the printed wiring board, then the manufacturing process is simple, but severe stress is generated due to the large CTE mismatch between the die and the PWB
Solution Approach 1:
The substrate is divided into two distinct pieces: a first piece (interposer substrate) that interfaces with the integrated circuit die and a second piece (mounting substrate) that interfaces with the printed wiring board. This segmentation allows each piece to be optimized for its specific interface, with the first piece having CTE matched to the die and the second piece having CTE matched to the PWB, thereby resolving the stress issue while maintaining manageable complexity through modular design.
Solution Approach 2:
The first substrate piece acts as an intermediary between the integrated circuit die and the printed wiring board. It provides a CTE-matched interface to the die, allowing the die to expand and contract thermally without generating excessive stress, while the second substrate piece provides the interface to the PWB. This intermediary structure mediates the CTE mismatch between the die and PWB.
2Reliability
If stress deflectors or voids are introduced in the substrate to allow floating bond pads, then thermal stress is reduced, but additional process steps are required and moisture trapping paths are created
Solution Approach 1:
The patent applies different CTE-matched materials to different regions of the substrate system. The first substrate piece uses a material with CTE matched to the integrated circuit die, while the second substrate piece uses a material with CTE matched to the printed wiring board. This local optimization of material properties allows stress reduction without requiring voids or floating bond pad structures, thereby avoiding additional manufacturing complexity and moisture trapping issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces stress in the semiconductor device by matching the thermal expansion coefficients of the base frame pieces with the die and the PWB, enhancing package reliability and enabling the use of thin film technologies and low K dielectrics while maintaining a compact form factor.
Implementation Method 1
The stress generated in a package can come from various sources. One of the sources of the stress is the difference in the coefficient of thermal expansions (CTE) of the different materials used for packaging. During each of such temperature variations, the different materials in the package expand or contract at different rates depending on whether the package is heated up or cooled down.
Implementation Method 2
a deformable connecting structures between the first and second pieces, which are able to compensate for the difference in thermal expansion
Implementation Method 3
which involves dispensing a liquid polymer adjacent to one edge of the assembled integrated circuit and allowing the polymer material to flow underneath the assembly due to capillary forces
Data Source
AI summary
A semiconductor package is disclosed. In one aspect, the package includes a base frame and a wiring substrate mounted on the base frame. The base frame has two pieces made of a material with respectively a first and a second coefficient of thermal expansion and connected to each other via resilient connecting structures. The wiring substrate has electric wiring tracks providing the electric connection between first and second bond pads, provided for being electrically connected to bond pads on respectively a die and a printed wiring board. The electrical wiring tracks have flexible parts provided to expand and contract along with the resilient connecting structures.