Semiconductor Package Structure with Dedicated Base Pad

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Solution Overview

Problem

Conventional bi-directional blocking transient voltage suppressors (TVS) face challenges with a floating base that leads to voltage variations and increased leakage currents due to charging and discharging currents, which are not effectively addressed in existing semiconductor package structures.

Innovation Solution

A semiconductor package structure comprising a chip unit, package unit, and electrode unit, where the package body covers the semiconductor chip's upper and peripheral surfaces, and electrode structures are formed on the lateral portions to electrically contact conductive pads, eliminating the need for a chip-carrying substrate and wire-bonding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a bi-directional blocking TVS is implemented with symmetric NPN/PNP configuration, then the breakdown voltage is identical, but the base becomes floating leading to voltage variations and increased leakage current

Engineering Contradiction:
Improvebreakdown voltage symmetryVSAvoidvoltage stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent extracts the base terminal from the floating state by connecting it to a dedicated base pad that is externally accessible. This allows the base to be properly biased or connected to a reference potential, eliminating the voltage variation issue while maintaining the symmetric NPN/PNP configuration for matched breakdown voltages.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a base pad as an intermediary element between the internal base terminal and the external circuit. This base pad serves as a mediator that provides a stable reference point, preventing the base from floating and reducing leakage current caused by voltage variations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional packaging with chip-carrying substrate and wire-bonding is used, then electrical connections are established, but the base remains floating causing leakage current issues

Engineering Contradiction:
Improveconnection establishmentVSAvoidleakage current
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the base connection from the conventional wire-bonding approach by providing a dedicated base pad on the package substrate. This allows the base to be connected through a low-impedance path directly to the substrate, eliminating the floating condition that causes leakage current while maintaining manufacturing simplicity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If the base is left floating to maintain symmetric configuration, then the TVS structure is simplified, but voltage variations over time increase

Engineering Contradiction:
ImproveTVS structureVSAvoidvoltage stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The patent segments the packaging structure by adding a dedicated base pad region on the substrate, separating the base connection function from the power and signal connections. This segmentation allows the base to be properly grounded or biased without complicating the overall TVS device structure, maintaining voltage stability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8846453B1Semiconductor package structure and method of manufacturing the same
Publication Date: 2014.09.30 INPAQ TECHNOLOGY CO LTD
  • US8846453B1 patent drawing
  • US8846453B1 patent drawing
  • US8846453B1 patent drawing

AI summary

A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads.