Semiconductor Package Binning via Wafer-Level Electrical Die Sorting
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Solution Overview
Problem
The existing methods of manufacturing semiconductor packages face challenges in simplifying the packaging and test processes without compromising reliability, as they require complex and time-consuming procedures for sorting and testing individual chips.
Innovation Solution
A method that involves electrical die sorting (EDS) to classify chips based on test bin items, followed by packaging and marking these items on a circuit substrate, allowing for the formation of individual packages that can be easily sorted and tested, utilizing a package sorter and tester to streamline the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual chips are sorted and tested separately after packaging, then testing accuracy is improved, but manufacturing time and process complexity increase significantly
Solution Approach 1:
The patent performs electrical die sorting (EDS) testing on chips while they are still in wafer form before packaging. This preliminary testing action classifies chips by performance characteristics (binning) in advance, so that when chips are packaged and later tested, the testing process is simplified and faster because chips are already sorted by their electrical characteristics.
Solution Approach 2:
The patent segments the testing process into two distinct phases: (1) wafer-level EDS testing to classify chips by electrical characteristics, and (2) post-packaging testing to verify packaged units. This segmentation allows each testing phase to focus on specific tasks, improving overall efficiency while maintaining accuracy.
2Reliability
If complex sorting procedures are used to classify chips by electrical characteristics, then product reliability is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent implements preliminary electrical die sorting (EDS) at the wafer level to classify chips by their electrical characteristics before packaging. This advance binning ensures that chips with similar electrical properties are grouped together, improving product reliability by ensuring consistent performance within each bin, while the automated EDS process keeps the complexity manageable.
Solution Approach 2:
The patent replaces manual or mechanical sorting methods with automated electrical die sorting (EDS) testing. This substitution uses electrical measurements to automatically classify chips by performance characteristics, reducing process complexity compared to manual inspection while improving reliability through precise electrical characterization.
3Productivity
If wafer-level testing is performed before sawing, then manufacturing efficiency is improved, but the ability to test individual packaged units is reduced
Solution Approach 1:
The patent segments the testing hierarchy into two levels: wafer-level EDS testing for efficiency (testing multiple chips simultaneously in electrical form) and packaged-unit testing for individual verification. This dual-level segmentation maintains manufacturing efficiency through wafer-level parallel testing while preserving the ability to test individual packaged units for final quality assurance.
Solution Approach 2:
The patent performs preliminary wafer-level EDS testing to classify chips by electrical characteristics before packaging, improving manufacturing efficiency. However, it maintains the capability for subsequent individual packaged unit testing to verify final product quality, thus balancing efficiency with individual unit testing capability.
Data Source
AI summary
A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.