Semiconductor Package Bond Finger Layout for EMI-Resistant Wiring

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Solution Overview

Problem

As semiconductor chips become more highly integrated, the reduction in size of chip pads and bond fingers leads to limitations in scaling down bond fingers, resulting in signal delay due to interference between signals, which is exacerbated by the difficulty in forming bond fingers and traces within the existing process techniques.

Innovation Solution

The semiconductor package design includes a package substrate with bond fingers arrayed in two columns, allowing for a maintained pitch and facilitating the formation of bond fingers without process limitations, while the chip pads are arranged in a matrix form to correspond to the bond fingers, enabling efficient electrical connection and reducing signal interference through a zigzag arrangement and electromagnetic shielding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If chip pads and bond fingers are scaled down to increase integration density, then the quantity of connections increases, but signal delay and electromagnetic interference worsen due to reduced pitch between bond fingers

Engineering Contradiction:
Improvequantity of connectionsVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a planar arrangement of bond fingers to a three-dimensional stacked configuration where bond fingers are arranged in multiple layers (first layer and second layer). This vertical dimensionality change allows increased connection density without reducing the horizontal pitch between bond fingers, thereby maintaining signal integrity while increasing the quantity of connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the bond finger connections into multiple independent layers, with each layer containing a column of bond fingers. This segmentation allows each layer to be independently optimized and reduces electromagnetic interference between adjacent connections by separating them in the vertical dimension, thus improving signal integrity while increasing total connection capacity.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If bond fingers are scaled down to increase integration density, then more bond fingers can be accommodated, but the difficulty of forming bond fingers and traces within existing process techniques increases

Engineering Contradiction:
Improvenumber of bond fingersVSAvoidease of forming bond fingers
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent utilizes the vertical dimension to stack multiple columns of bond fingers at different heights (first layer and second layer). This approach increases the number of bond fingers without requiring further miniaturization in the planar direction, thus avoiding the manufacturing difficulties associated with scaling down bond finger dimensions while still achieving higher integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If bond fingers are arranged in a single layer to simplify structure, then device complexity is reduced, but signal interference increases due to closer spacing between adjacent bond fingers

Engineering Contradiction:
Improvestructural complexityVSAvoidelectromagnetic interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent resolves the contradiction by introducing a vertical layering dimension, arranging bond fingers in multiple stacked columns rather than a single planar layer. This three-dimensional arrangement increases the effective spacing between adjacent bond fingers by utilizing the vertical dimension, thereby reducing electromagnetic interference while maintaining relatively simple manufacturing processes and device structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250014999A1Semiconductor packages
Publication Date: 2025.01.09 SK HYNIX INC
  • US20250014999A1 patent drawing
  • US20250014999A1 patent drawing
  • US20250014999A1 patent drawing

AI summary

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.