Semiconductor Package Pad Layout for Routing Space
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Solution Overview
Problem
In semiconductor packaging, the dense arrangement of wiring pads on semiconductor chips leads to space constraints, particularly when stacking chips, making it challenging to secure routing areas and efficiently connect conductive wires.
Innovation Solution
The semiconductor package design includes bonding pads and non-bonding pads arranged in distinct columns, with non-bonding pads not connected to conductive wires, allowing for secure routing area placement and test signal functionality, and enabling cascading chip stacks without overlapping wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are densely arranged on the semiconductor chip to increase integration density, then device functionality is improved, but routing space becomes insufficient and wiring overlap occurs when stacking chips
Solution Approach 1:
The pad area is segmented into two distinct groups: bonding pads arranged in a first column for electrical connection, and non-bonding pads arranged in a second column for testing only. This segmentation separates the routing paths, preventing wiring overlap while maintaining high pad density on the chip surface.
Solution Approach 2:
The solution transitions from a single-column pad arrangement to a multi-column layout, utilizing the vertical dimension of the chip surface more effectively. By arranging pads in multiple columns with distinct functions, the design maximizes space utilization without compromising routing availability.
2Ease of manufacture
If bonding pads are arranged in a single column to simplify wiring, then manufacturing is easier, but test signal accessibility is limited
Solution Approach 1:
The pad structure is divided into bonding pads for manufacturing connections and non-bonding pads for testing purposes. This segmentation allows bonding pads to maintain simple columnar arrangement for ease of wiring, while non-bonding pads provide additional accessibility points for comprehensive test signal application.
Solution Approach 2:
The non-bonding pads serve multiple functions: they can receive test signals independently, work in conjunction with bonding pads for comprehensive testing, and maintain the overall structural simplicity of the columnar arrangement. This multi-functionality enhances test accessibility without complicating the manufacturing process.
3Ease of operation
If non-bonding pads are completely exposed for testing, then test signal accessibility is improved, but chip stacking efficiency decreases
Solution Approach 1:
Different regions of the pad structure have different exposure characteristics: non-bonding pads are positioned to be accessible for test signal application, while bonding pads remain exposed for electrical connection. The upper chip selectively covers certain non-bonding pads after testing, creating local quality variations that satisfy both testing and stacking requirements.
Solution Approach 2:
Testing operations are performed on non-bonding pads before final chip stacking. This preliminary action allows complete accessibility during testing, after which the upper chip can cover the non-bonding pads to improve stacking efficiency for subsequent operations.
Data Source
AI summary
A semiconductor package includes a substrate including connection pads, a first semiconductor, and conductive wires. The first semiconductor chip is stacked on the substrate and includes bonding pads, non-bonding pads, and a routing area that is provided adjacent a center of an edge of the first semiconductor chip. The conductive wires are connected to the bonding pads and the connection pads. The bonding pads are disposed to form at least one column in a direction extending along the edge of the first semiconductor chip and are not disposed in the routing area. The non-bonding pads are disposed to form a column different from the at least one column formed by the bonding pads.