Stacked Semiconductor Package Bonding Pad Direct Contact
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Solution Overview
Problem
The increasing demand for high-speed, highly integrated semiconductor packages has not been adequately met by existing technologies, particularly in terms of operation reliability for stacked semiconductor chips.
Innovation Solution
A semiconductor package design featuring a first semiconductor chip with a wiring structure, through electrodes, and bonding pads, stacked on a second semiconductor chip with a similar structure, where the bonding pads are directly connected to ensure electrical contact and enhance signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips are stacked to achieve high integration and miniaturization, then the functionality and performance are improved, but the operation reliability deteriorates due to increased complexity of electrical connections between chips
Solution Approach 1:
The bonding pad structure is segmented into distinct functional zones: a first bonding pad region on the first chip and a second bonding pad region on the second chip, with the through electrode providing a separate vertical connection path. This segmentation allows independent optimization of each bonding interface while maintaining overall connection reliability.
Solution Approach 2:
The through electrode acts as an intermediary element that penetrates the first semiconductor chip to establish direct electrical connection between the first bonding pad and the second bonding pad. This mediator structure eliminates the need for complex lateral wiring paths through the chip substrate, thereby improving signal integrity and reducing connection points of failure.
2Ease of manufacture
If conventional wiring structures are used in stacked chips, then manufacturing is easier, but signal integrity and power integrity deteriorate due to indirect electrical paths
Solution Approach 1:
Instead of routing signals laterally through the chip substrate and then vertically to adjacent chips, the invention inverts the connection approach by establishing vertical connections first through the chip substrate using through electrodes, and then routing signals horizontally at the bonding pad level. This inversion creates shorter, more direct electrical paths that improve signal integrity and reduce interference.
3Reliability
If multiple wiring layers are added to improve electrical connections between stacked chips, then connection reliability is improved, but device complexity increases
Solution Approach 1:
The invention transitions from two-dimensional planar wiring structures to three-dimensional vertical wiring structures by implementing through electrodes that penetrate the chip substrate. This dimensional change allows electrical connections to be established in the vertical dimension, reducing the need for complex multi-layer lateral wiring and simplifying the overall wiring architecture while improving connection reliability.
Data Source
AI summary
A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.