Semiconductor Package Stack Structure for Stable Multi-Chip Bonding
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Solution Overview
Problem
Existing multi-chip semiconductor packages face challenges in achieving enhanced electrical characteristics and structural stability due to variations in bonding quality between stacked chips.
Innovation Solution
The semiconductor package design includes a buffer die with logic devices and memory die stack structures, where each memory die stack consists of base core dies and middle core dies stacked vertically, with specific mold layers and bonding patterns to enhance electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked vertically to increase integration density, then the quantity of functional components increases, but the bonding quality variations between chips deteriorate structural stability
Solution Approach 1:
The patent divides the stack into multiple groups, where chips within each group are bonded using HCB process, and groups are bonded to each other using TCB process. This segmentation allows different bonding methods to be applied to different sections, addressing the variability in bonding quality across the entire stack.
Solution Approach 2:
The patent applies different bonding processes (HCB and TCB) to different locations in the stack. HCB is used for chips within groups while TCB is used for bonding between groups, creating localized bonding solutions that optimize quality consistency across the entire multi-chip structure.
2Reliability
If different bonding processes are used for different chip groups, then bonding quality consistency improves, but device complexity increases
Solution Approach 1:
The patent segments the bonding process into two distinct stages: HCB for intra-group chip bonding and TCB for inter-group group bonding. This segmentation makes the complex multi-chip assembly manageable by breaking it into standardized, repeatable units.
Solution Approach 2:
The patent organizes chips into a hierarchical structure with groups stacked vertically, adding an organizational dimension to the bonding process. This allows systematic application of different bonding methods at different hierarchical levels, reducing overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the electrical characteristics and structural stability of the semiconductor package by ensuring consistent and robust bonding between chips, thereby enhancing the overall performance and reliability of the package.
Implementation Method 1
The lower semiconductor chip stack structure and the upper semiconductor chip stack structure may be bonded to each other by a conductive bump
Implementation Method 2
A bonding layer containing a conductive pattern is disposed between the chips, and electrically connects the chips with each other
Data Source
AI summary
A semiconductor package includes a buffer die, memory die stack structures sequentially stacked on the buffer die in a vertical direction, each of which includes a base core die and middle core dies stacked on the base core die in the vertical direction, a first mold layer on the base core die of each of the memory die stack structures and on sidewalls of the middle core dies, and a second mold layer on the buffer die, on sidewalls of the base core dies, and on a sidewall of the first mold layer. The buffer die has a first planar area, the base core die has a second planar area smaller than the first planar area, and each of the middle core dies has a third planar area smaller than the second planar area.