Semiconductor Package Bonding Wire Loop Inductance Reduction
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Solution Overview
Problem
In semiconductor packages, particularly in DRAMs, the existing PoP structure with a 4:1 signal to ground (SG) ratio leads to longer interconnects for command and address signals, resulting in high parasitic inductance, noise, and jitter due to low power feeding capability, which is exacerbated by the LPDDR2 standard's double data rate requirements.
Innovation Solution
The implementation of a semiconductor package with a 1:1 SG ratio by alternately arranging Vdd and Vss auxiliary pads between address signal pads, using Redistribution Layer (RDL) technology for interconnects, and positioning Vdd and Vss bond fingers next to signal bond fingers to reduce loop inductance and improve signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 4:1 signal to ground (SG) ratio is used in the PoP structure, then the package structure is simpler and easier to manufacture, but the interconnect length increases resulting in high parasitic inductance and noise
Solution Approach 1:
The patent applies local quality by changing the SG ratio from 4:1 to 1:1 specifically in the bond finger arrangement and pad layout. This localized structural modification reduces the loop area and interconnect length for command and address signals, thereby reducing parasitic inductance and improving signal quality without requiring a complete redesign of the entire package structure
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple bond finger pairs in the Z-direction. This allows multiple power and ground bonds to be formed in close proximity, effectively reducing the loop area in three-dimensional space and minimizing parasitic inductance while maintaining a compact package footprint
2Device complexity
If longer interconnects are used for command and address signals in the PoP structure, then the package layout is simpler, but parasitic inductance and noise increase
Solution Approach 1:
The patent introduces asymmetry in the bond finger configuration by placing power and ground bond fingers in alternating positions specifically for command and address signals. This asymmetric arrangement creates smaller current loops and shorter interconnect paths compared to symmetric configurations, thereby reducing parasitic inductance while maintaining manufacturing simplicity
3Reliability
If the SG ratio is reduced to 1:1 with alternating Vdd and Vss pads, then loop inductance is reduced and signal quality improves, but the pad arrangement complexity increases
Solution Approach 1:
The patent segments the pad array into alternating power (Vdd) and ground (Vss) pads, creating a systematic 1:1 SG ratio pattern. This segmentation approach, while increasing pad arrangement complexity, effectively reduces loop inductance by minimizing the area enclosed by power and ground current loops, thereby improving signal transmission quality for command and address signals
Data Source
AI summary
A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.