Semiconductor Package Bridge Chip Proximity Communication
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the yield and quality of semiconductor device packages due to fragility and potential damage during assembly, particularly when chips are directly handled or subjected to stress, leading to cracks and invisible flaws that compromise the integrity of the IC package.
Innovation Solution
A semiconductor device package design that includes a first and second substrate, active chips, and a bridge chip, where the active chips are electrically connected to the first substrate and the bridge chip is mechanically and electrically connected to the second substrate, allowing for proximity communication without direct handling, using a connection structure that combines the substrates without requiring additional tools to handle the chips during assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are directly handled by suction nozzle during assembly, then assembly process is simple, but chip damage occurs due to stress and fragility
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary component that holds multiple chips during assembly. Instead of directly handling fragile chips with suction nozzles, the carrier substrate serves as a robust mediator that can be gripped and positioned without stressing the chips. The chips are mounted on the carrier substrate first, and the entire carrier-substrate-chip assembly is then handled as a single unit during the assembly process, eliminating direct contact between suction nozzles and chips while maintaining assembly simplicity.
2Adaptability or versatility
If circuit density on IC package is increased, then functionality is improved, but mechanical and electrical properties become harder to maintain
Solution Approach 1:
The patent segments the IC package into multiple functional layers and components: carrier substrate, active chips, intermediate substrate, and cap substrate. This segmentation allows each layer to be optimized independently - the carrier substrate provides mechanical support for high-density chip arrangement, the intermediate substrate handles electrical interconnections, and the cap substrate provides protection. By dividing the package structure into specialized segments, the design can accommodate higher circuit density while maintaining mechanical strength and electrical performance through dedicated functional zones.
3Manufacturing precision
If chips are subjected to stress during assembly, then positioning is achieved, but cracks and invisible flaws occur compromising package integrity
Solution Approach 1:
The patent implements preliminary action by pre-mounting chips onto a carrier substrate before the main assembly process. The carrier substrate serves as a preliminary platform that stabilizes chips and distributes assembly stresses away from the chip bodies. During subsequent assembly steps, the carrier substrate (with chips already attached) is handled as a unified structure, allowing precise positioning to be achieved through carrier substrate manipulation rather than direct chip manipulation, thereby preventing stress-induced cracks and flaws while maintaining manufacturing precision.
Data Source
AI summary
A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.