Semiconductor Package Bridge Die Layout for Shorter Interconnect Paths
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and performance due to long electrical paths in metal posts, which increase turn-around time and yield degradation, and result in larger package sizes when stacking semiconductor packages vertically.
Innovation Solution
A semiconductor package design that includes a first redistribution layer structure, semiconductor dies, conductive posts, an interposer with a bridge die, and a substrate to electrically connect the dies, reducing the need for long metal posts and minimizing package size by using a bridge die to connect upper and lower structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal posts are used to electrically connect upper and lower structures in vertically stacked semiconductor packages, then electrical connection is achieved, but the electrical path length increases leading to longer turn-around time and yield degradation
Solution Approach 1:
The patent transitions from horizontal metal post connections to vertical through-silicon via (TSV) connections by changing the dimensional approach. TSVs provide direct vertical electrical pathways through the substrate, eliminating the need for long horizontal metal posts and reducing the electrical path length, thereby decreasing turn-around time and improving yield.
Solution Approach 2:
The patent introduces an interposer structure as an intermediary between the upper and lower semiconductor packages. The interposer contains TSVs that provide direct electrical connection pathways, acting as a mediator that eliminates the need for long metal posts while enabling vertical stacking and reducing overall electrical path length.
2Reliability
If metal posts are positioned between semiconductor dies arranged side by side to enable vertical stacking, then electrical connection is achieved, but the package size increases
Solution Approach 1:
The patent moves the electrical connection approach from the horizontal plane (metal posts between side-by-side dies) to the vertical dimension (TSVs through the substrate). This dimensional change allows direct vertical connections, eliminating the need for lateral metal post extensions and reducing the overall package footprint.
Solution Approach 2:
The patent implements a nested structure where the interposer with TSVs is positioned within the vertical stacking arrangement of semiconductor packages. The TSVs are nested within the substrate thickness, providing electrical connections without increasing the lateral package dimensions, thereby minimizing package size while maintaining connectivity.
Data Source
AI summary
A semiconductor package includes: a first redistribution layer structure; a first semiconductor die disposed on the first redistribution layer structure; a second semiconductor die disposed adjacent to the first semiconductor die on the first redistribution layer structure; a molding material positioned on the first redistribution layer structure, and covering the first semiconductor die and the second semiconductor die; a bridge die positioned on the molding material, the first semiconductor die, and the second semiconductor die, and electrically connecting the first semiconductor die and the second semiconductor die to each other; a substrate positioned on the molding material, the first semiconductor die, and the second semiconductor die, and at least partially surrounding the bridge die; and a second redistribution layer structure disposed on the bridge die and the substrate.