Semiconductor Package Bridge Structure for Dense Fan-Out Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages, such as CoWoS structures, are inadequate in achieving optimal integration density and size reduction for advanced applications like cloud computing and data centers.
Innovation Solution
A semiconductor package design featuring chiplets on fan-out substrates (CoFoS) with interposers and bridge structures for electrical connections, utilizing multiple redistribution layers and dielectric encapsulations to enhance integration and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If existing CoWoS structures are used for advanced products, then integration density can be improved, but package size reduction is insufficient
Solution Approach 1:
The patent segments the semiconductor package into multiple independent components: chiplets (compute die, memory die, I/O die) mounted on a substrate, with each chiplet being a separate functional unit. This segmentation allows for optimized individual chiplet sizes and enables the substrate to provide fan-out routing that reduces the overall package footprint while maintaining high integration density through multiple chiplets working together.
Solution Approach 2:
The patent transitions from traditional 2D planar interconnection to 3D vertical stacking with multiple redistribution layers (RDL0, RDL1, RDL2) and through-substrate vias (TSVs). This dimensional change enables signals to route through the substrate thickness rather than requiring large lateral distances, thereby reducing package area while maintaining connectivity between numerous chiplets.
2Quantity of substance
If multiple redistribution layers and dielectric encapsulations are added to enhance integration, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming the substrate with complete fan-out routing, multiple RDL structures, and TSVs before mounting the chiplets. The substrate is prepared in advance with all necessary interconnection structures, allowing chiplets to be simply mounted onto pre-configured pads without requiring complex post-assembly routing or additional processing steps.
Solution Approach 2:
The substrate acts as an intermediary component that provides the complex fan-out routing and redistribution functionality, while the chiplets remain simple functional blocks. This intermediary substrate absorbs the manufacturing complexity of multiple RDLs and TSVs, allowing the chiplets themselves to remain simple and enabling modular assembly where the complex substrate and simple chiplets can be manufactured independently and then combined.
3Productivity
If fan-out routing is implemented to improve connectivity, then electrical routing efficiency improves, but package area increases
Solution Approach 1:
The patent uses the substrate thickness dimension to route signals vertically through TSVs and across multiple RDL layers, rather than requiring long lateral paths. This 3D routing approach allows signals to reach their destinations through the substrate depth, dramatically reducing the lateral footprint required for fan-out connections and enabling efficient electrical routing within a compact package area.
Solution Approach 2:
The patent segments the routing function across multiple independent layers (RDL0, RDL1, RDL2) and vertical TSV pathways, allowing different signal types and destinations to be routed through different spatial channels. This layered segmentation enables high-density interconnection without requiring large lateral distances, as each layer provides dedicated routing paths that can be optimized independently.
Data Source
AI summary
A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.