Semiconductor Package Bridge Wiring for Dense Multi-Chip Integration

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing miniaturized, multifunctional, high-performance, and high-capacity semiconductor products at low costs, particularly in achieving high-density integration of chips within semiconductor packages.

Innovation Solution

A semiconductor package design incorporating a fan-in-chip structure with bridge wiring and redistribution structures, including a bridge wiring layer on the rear surface of a chip, and redistribution elements extending between the fan-in and fan-out regions, allowing for efficient electrical connections and high-density integration of additional chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional chip integration methods are used, then manufacturing process is simple, but chip integration density is low

Engineering Contradiction:
Improvechip integration densityVSAvoidpackage structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar chip arrangement to three-dimensional stacked configuration, utilizing vertical space above and below the substrate to increase chip integration density. Multiple chips are arranged in stacked layers connected through redistribution structures, effectively moving from two-dimensional to three-dimensional space utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The package structure is divided into distinct functional regions including fan-in region, fan-out region, and intermediate region. Each region contains specific components and wiring structures, allowing independent optimization and manufacturing of each segment while achieving high overall integration density.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If chip integration density is increased, then product capacity increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvechip integration densityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

Redistribution structures and wiring patterns are pre-formed on the substrate before chip mounting. Alignment marks and positioning features are prepared in advance to guide precise chip placement. This preliminary preparation ensures that high-density integration achieves the required alignment precision during assembly.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If bridge wiring structure is added, then electrical connection efficiency improves, but device complexity increases

Engineering Contradiction:
Improveelectrical connection efficiencyVSAvoidwiring structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Redistribution structures serve as intermediary elements between chips and external connections. These intermediate wiring layers reroute electrical signals efficiently, reducing the number of direct long-distance connections needed. The bridge wiring structure acts as a mediator that optimizes signal paths while managing complexity through systematic routing patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240258242A1Semiconductor package
Publication Date: 2024.08.01 SAMSUNG ELECTRONICS CO LTD
  • US20240258242A1 patent drawing
  • US20240258242A1 patent drawing
  • US20240258242A1 patent drawing

AI summary

A semiconductor package includes a package body, a fan-in-chip structure (FICS) in the package body, a first redistribution structure, and a second redistribution structure. The FICS includes a first chip having a front surface and a rear surface, a bridge wiring structure including a bridge wiring layer on the rear surface of the first chip, and a bridge pad electrically connected to the bridge wiring layer. The first redistribution structure is on a bottom surface of the package body and the front surface of the first chip and includes a first redistribution element. The second redistribution structure is on a top surface of the package body and the rear surface of the first chip and includes a second redistribution element electrically connected to the bridge wiring structure.