Semiconductor Package Interconnect Structure for Brittle Solder Joints
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Solution Overview
Problem
The reliability of semiconductor package devices is compromised due to the brittleness of intermetallic compounds formed through reflow soldering, which can lead to mechanical stress and failure in electronic devices.
Innovation Solution
A semiconductor package device is designed with a circuit substrate, a chip, an auxiliary structure between the terminal end and the conductive pad, and a protective layer surrounding the chip, where the auxiliary structure is formed using a solid solution compound that enhances binding strength and reliability, and the protective layer improves durability against environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reflow soldering process is used to connect chip and circuit substrate, then electrical connection is achieved, but the intermetallic compound formed is brittle and easily broken affecting reliability
Solution Approach 1:
The patent introduces an auxiliary structure as an intermediary component between the chip and circuit substrate. This auxiliary structure includes a first auxiliary layer formed on the circuit substrate and a second auxiliary layer formed on the chip, which are mutually embedded to create a mechanical interlocking connection. This mediator structure replaces the brittle intermetallic compound connection with a physically interlocked joint that resists mechanical stress while maintaining electrical connectivity through conductive patterns.
Solution Approach 2:
The auxiliary structure employs composite material construction with multiple layers having different properties. The first auxiliary layer and second auxiliary layer are composed of different materials with complementary characteristics - one layer provides mechanical support and embedding while the other provides electrical conductivity and stress distribution. This composite approach creates a connection structure that combines the benefits of mechanical strength and electrical functionality, overcoming the limitations of single-material intermetallic compounds.
2Adaptability or versatility
If stacked chips and circuit substrates are connected by reflow soldering, then functional integration is achieved, but mechanical stress causes connection failure
Solution Approach 1:
The connection structure is segmented into multiple functional layers: the first auxiliary layer on the circuit substrate, the second auxiliary layer on the chip, and their mutual embedding interface. This segmentation allows each layer to be optimized for specific functions - mechanical support, electrical conductivity, and stress absorption - rather than requiring a single material to perform all functions simultaneously. The segmented structure distributes mechanical stress across multiple interfaces, preventing concentrated stress points that lead to failure.
Solution Approach 2:
The patent changes the physical and chemical parameters of the connection structure by using auxiliary layers with different material compositions, thicknesses, and mechanical properties compared to traditional solder joints. The auxiliary layers are designed with specific elastic moduli, yield strengths, and thermal expansion coefficients that differ from conventional intermetallic compounds, allowing the connection to accommodate thermal cycling and mechanical stress without failure while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the binding strength between the chip and the circuit substrate, enhances signal transmission quality, and increases the reliability of the semiconductor package device by reducing mechanical stress and environmental vulnerabilities.
Implementation Method 1
an auxiliary structure disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure
Data Source
AI summary
A semiconductor package device is provided. The semiconductor package device includes a circuit substrate having a first terminal end; a chip disposed on the circuit substrate and having a conductive pad; an auxiliary structure disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; and a protective layer disposed on the circuit substrate and surrounding the chip, wherein the width of the first terminal end is greater than or equal to the width of the auxiliary structure.