Semiconductor Package Buffer Rings for UBM Edge Crack Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing stress-induced cracking at the edges of under-bump metallizations due to coefficient of thermal expansion (CTE) mismatch between semiconductor devices and interposers, which affects the reliability of integrated circuit packages.
Innovation Solution
A redistribution structure with dielectric layers and metallization patterns is formed, including a buffer layer or buffer rings around under-bump metallizations to mitigate stress, using materials like molding compounds and photosensitive polymers, and a surface treatment process to enhance bonding strength between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor devices and interposers are directly connected without buffer features, then the device complexity is reduced, but stress-induced cracking occurs at the edges of under-bump metallizations due to CTE mismatch
Solution Approach 1:
A buffer layer or buffer rings are introduced as intermediary structures between the interposer and the under-bump metallization. These buffer features have intermediate CTE values that gradually transition between the interposer and UBM, reducing the abrupt CTE mismatch that causes stress concentration and cracking at the UBM edges.
Solution Approach 2:
The CTE parameter is gradually changed across the buffer layer thickness, creating a gradient from the interposer CTE to the UBM CTE. This parameter transition reduces thermal stress by distributing the expansion/contraction differences across multiple layers rather than concentrating it at a single interface.
2Reliability
If buffer layers are added around under-bump metallizations, then stress from CTE mismatch is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The buffer layer is formed on the interposer surface before the under-bump metallization is deposited. This preliminary formation allows the buffer layer to be integrated into the manufacturing process flow, and its surface can be prepared in advance to receive the UBM deposition, reducing overall process complexity.
Solution Approach 2:
Buffer rings are formed only in specific locations around the UBM edges where stress concentration occurs, rather than covering the entire UBM surface. This localized approach reduces material usage and simplifies the patterning process while still providing stress relief where it is most needed.
3Reliability
If the buffer layer completely covers the upper dielectric layer, then stress buffering is maximized, but the bonding strength between layers may be reduced
Solution Approach 1:
The buffer layer is selectively removed or not formed in certain regions to expose the upper dielectric layer, creating areas of different buffer coverage. This allows optimization of stress buffering in some regions while maintaining strong bonding in other regions where the dielectric layer provides better adhesion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of cracking and improves the reliability of integrated circuit packages by buffering stress caused by CTE mismatch, enhancing bonding strength and manufacturing efficiency.
Implementation Method 1
forming dangling bonds on an upper dielectric layer of the redistribution structure by treating the upper dielectric layer
Implementation Method 2
forming a buffer layer on the upper dielectric layer and on an under-bump metallization of the redistribution structure by bonding a buffer material to the dangling bonds
Data Source
AI summary
Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.