Semiconductor Package Buffer Layer and Shielding for Impact Resistance
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Solution Overview
Problem
Semiconductor packages face challenges with impact resistance, thermal shock, and electromagnetic interference (EMI) during operation and manufacturing, leading to potential malfunctions and interference with nearby devices.
Innovation Solution
A semiconductor package design featuring a chip with a buffer layer, wiring patterns, an insulating layer, and a mold layer, along with a metal shielding layer, where the insulating and mold layers have matching thermal expansion coefficients and are formed from non-photosensitive materials, providing enhanced impact resistance, heat dissipation, and EMI shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional semiconductor package structure is used, then the manufacturing process is simple, but the package has poor impact resistance and thermal shock resistance
Solution Approach 1:
The patent employs a multi-layer composite structure consisting of a chip, buffer layer, insulating layer, mold layer, and metal shielding layer. Each layer is made of different materials optimized for specific functions: the buffer layer (e.g., epoxy resin with filler) provides mechanical support and thermal management, the insulating layer (e.g., polyimide or benzocyclobutene) provides electrical insulation, and the metal shielding layer provides EMI shielding. This composite approach enhances impact and thermal shock resistance while maintaining manufacturing feasibility through established layer-by-layer fabrication processes.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the package. The buffer layer is positioned directly on the chip to provide localized mechanical support, the mold layer surrounds the chip periphery for edge protection, and the metal shielding layer is strategically placed to provide EMI shielding where needed. This localized optimization allows the package to achieve enhanced strength without uniformly increasing overall complexity.
2Temperature
If heat is accumulated during operation, then the device can operate continuously, but operation failures and malfunctions occur
Solution Approach 1:
The patent carefully selects materials with compatible coefficients of thermal expansion (CTE) to minimize thermal stress during temperature cycling. The buffer layer and mold layer are designed with CTE values matched to the chip substrate, preventing delamination and structural failure during thermal shock. This thermal expansion management ensures reliable operation under continuous heat generation while maintaining structural integrity.
Solution Approach 2:
The buffer layer acts as an intermediary between the chip and the external environment, providing thermal management functionality. It conducts heat away from the chip while providing mechanical support and electrical insulation. The mold layer further mediates thermal dissipation to the surrounding environment. This intermediary structure enables continuous operation by managing heat accumulation without directly contacting the chip, thereby maintaining reliability.
3Object-generated harmful factors
If electromagnetic interference is generated during operation, then the device can function, but nearby devices malfunction
Solution Approach 1:
The patent converts the potentially harmful electromagnetic interference generated by the chip into a controlled phenomenon by enclosing it within the mold layer and metal shielding layer. The metal shielding layer, made of conductive material, acts as a Faraday cage that traps electromagnetic fields inside the package, preventing them from interfering with nearby devices. This approach transforms the harmful EMI into a contained field that can be managed and directed, thereby protecting external devices while maintaining internal functionality.
4Ease of manufacture
If the insulating layer and mold layer are formed from materials with different thermal expansion coefficients, then manufacturing is easier, but thermal shock resistance deteriorates
Solution Approach 1:
The patent carefully controls the material selection parameters, specifically the coefficient of thermal expansion (CTE), to ensure compatibility between the insulating layer and mold layer. By selecting materials with CTE values within a specific range and matching them to the chip substrate, the patent achieves both manufacturability and thermal shock resistance. This parameter optimization allows the use of standard manufacturing processes while ensuring structural stability under thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the package's resistance to physical impacts and thermal shocks, improves heat dissipation, and effectively shields against electromagnetic interference, ensuring operational stability and reliability.
Implementation Method 1
The insulating layer and the mold layer may be formed of materials having coefficients of thermal expansion whose difference is in a range of 0 to 25 ppm/° C.
Implementation Method 2
a metal shielding layer formed on the other surface of the chip, which is a surface opposite to one surface of the chip, and the other surface of the mold layer
Implementation Method 3
Each of the insulating layer and the mold layer may include a filler
Data Source
AI summary
A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.