Semiconductor Package Double Adhesive Structure for Bump Bonding Reliability

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Solution Overview

Problem

Defective bonding of semiconductor chips due to adhesive layer and bump defects degrades the reliability of semiconductor packages, necessitating improved bonding performance.

Innovation Solution

A semiconductor package design featuring a double adhesive layer structure, where the first adhesive layer surrounds the bump and conductive pads with a narrower width than the second adhesive layer, utilizing different materials for each layer to enhance bonding reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single adhesive layer is used to bond the semiconductor chip, then the bonding performance is insufficient due to defects in adhesive layers and bumps, but using a double adhesive layer structure increases the complexity of the bonding structure

Engineering Contradiction:
Improvebonding reliabilityVSAvoidadhesive layer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding structure is segmented into two distinct adhesive layers (first adhesive layer and second adhesive layer) with different materials and functions. The first adhesive layer contacts the substrate and provides initial bonding, while the second adhesive layer contacts the semiconductor chip and ensures final bonding reliability, thereby resolving the technical contradiction by dividing the bonding function into separate stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite materials by using two different adhesive materials with different properties in the two adhesive layers. This allows optimization of each layer's material characteristics for its specific function, improving overall bonding reliability while managing the complexity through functional differentiation.

Inventive Principle:
Principle #40Composite materials

2Reliability

If the first adhesive layer has a width equal to or larger than the semiconductor chip, then it provides sufficient bonding area, but it increases the horizontal width of the package structure

Engineering Contradiction:
Improvebonding area coverageVSAvoidpackage horizontal width
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The first adhesive layer is designed with a width smaller than the semiconductor chip's horizontal width, creating a localized bonding structure. This local quality approach concentrates the adhesive material where most needed (under and around the bump) while reducing the overall package width, resolving the contradiction between bonding coverage and package size.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the first adhesive layer has higher hardness to maintain shape during bonding, then bonding precision is improved, but the adhesive strength may be reduced

Engineering Contradiction:
Improveshape maintenance precisionVSAvoidadhesive bonding strength
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The bonding function is segmented between two adhesive layers with different hardness characteristics. The first adhesive layer has higher hardness to maintain shape precision during the bonding process, while the second adhesive layer compensates for adhesive strength, ensuring overall bonding reliability without requiring the first layer to have both high hardness and high adhesive strength simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the material parameters (hardness) of the first adhesive layer to optimize shape maintenance during bonding. By adjusting this parameter and compensating with the second adhesive layer, the system achieves both shape precision and bonding strength through parameter optimization across multiple components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240162184A1Semiconductor package
Publication Date: 2024.05.16 SAMSUNG ELECTRONICS CO LTD
  • US20240162184A1 patent drawing
  • US20240162184A1 patent drawing
  • US20240162184A1 patent drawing

AI summary

A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.