Semiconductor Package Spacing Pattern to Prevent Bump Bridging

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and preventing bridging between conductive bumps during the bonding process of semiconductor packages, particularly in Package-on-Package (PoP) technology, where maintaining precise spacing and preventing solder overflow is crucial for efficient packaging.

Innovation Solution

A semiconductor package design that incorporates a spacing pattern with a melting temperature higher than the solder cap, formed from materials like copper, nickel, or polyimide, which acts as spacers to maintain a predetermined gap between substrates and prevent bridging, while also serving as a reference plane for horizontal calibration during the reflow process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bonding process is performed without spacing structures, then the manufacturing process is simpler, but solder overflow and bridging between conductive bumps occur

Engineering Contradiction:
Improvebonding reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The spacing pattern is formed on the first substrate before the bonding process. This preliminary structure maintains a predetermined gap between the first and second substrates during bonding, preventing solder overflow and bridging between conductive bumps while ensuring reliable bonding connections.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacing pattern acts as an intermediary element between the first and second substrates. It mediates the bonding process by maintaining proper spacing and preventing direct contact between adjacent conductive bumps, thus avoiding short circuits while allowing the bonding to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the spacing pattern is made from materials with low melting temperature, then the reflow process is easier, but the spacing pattern cannot maintain structural integrity during bonding

Engineering Contradiction:
Improvespacing precisionVSAvoidreflow process ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The spacing pattern is constructed from materials with specific melting temperatures higher than the solder cap material. This parameter selection ensures the spacing pattern maintains its structural integrity and predetermined gap dimensions during the reflow bonding process, while still allowing the solder to melt and form connections.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The spacing pattern effectively prevents solder overflow and bridging between conductive bumps, ensuring reliable bonding and maintaining precise spacing, thereby enhancing the integration density and stability of semiconductor packages.

Implementation Method 1

a spacing pattern with a melting temperature higher than the solder cap, formed from materials like copper, nickel, or polyimide, which acts as spacers to maintain a predetermined gap between substrates

Methodology Applied
Scientific EffectMelting temperature differential: Melting

Implementation Method 2

serving as a reference plane for horizontal calibration during the reflow process

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240128218A1Semiconductor package and manufacturing method thereof
Publication Date: 2024.04.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240128218A1 patent drawing
  • US20240128218A1 patent drawing
  • US20240128218A1 patent drawing

AI summary

A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.