Semiconductor Package Buried Wiring Layout for Thin Heat-Dissipating RDL
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Solution Overview
Problem
The existing semiconductor packages face challenges with increased thickness due to stacked upper redistribution wiring layers and deteriorated heat dissipation performance due to the relatively low thermal conductivity of sealing members.
Innovation Solution
A semiconductor package design that includes a lower redistribution wiring layer, a semiconductor chip, a sealing member, and an upper redistribution wiring layer with buried wirings in recesses on the sealing member's surface, which are electrically connected to through vias, and additional upper redistribution wirings in insulating layers, reducing the thickness and enhancing heat dissipation by utilizing materials with higher thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If upper redistribution wirings are stacked in multiple layers, then electrical connection functionality is improved, but package thickness increases
Solution Approach 1:
The patent transitions from vertical stacking of redistribution wirings to a planar layout by forming recesses in the sealing member. Buried wirings are placed horizontally within these recesses, converting a three-dimensional vertical arrangement into a two-dimensional planar configuration. This dimensional change allows multiple wiring paths to coexist without increasing package thickness, while still providing comprehensive electrical connection functionality between the semiconductor chip and external terminals.
2Reliability
If sealing member is used to cover semiconductor chip, then chip protection is improved, but heat dissipation performance deteriorates due to low thermal conductivity
Solution Approach 1:
The patent creates a composite structure by embedding buried wirings made of high thermal conductivity materials (such as copper or aluminum) within recesses of the sealing member. This composite design combines the protective function of the sealing member with the heat dissipation capability of the metal wirings. The buried wirings act as thermal pathways, conducting heat away from the semiconductor chip while the sealing member continues to provide mechanical protection and environmental sealing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the overall package thickness and improves heat dissipation performance by using buried wirings with higher thermal conductivity than the sealing member, addressing the limitations of existing designs.
Implementation Method 1
improved heat dissipation characteristics... using buried wirings with higher thermal conductivity than the sealing member
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer including first redistribution wiring, a semiconductor chip on the lower redistribution wiring layer and electrically connected to the first redistribution wirings, a sealing member on the semiconductor chip on the lower redistribution wiring layer, a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings, an upper redistribution wiring layer on the sealing member and having second redistribution wirings electrically connected to the plurality of through vias. The second redistribution wirings includes buried wirings that are buried in a plurality of recesses formed in an upper surface of the sealing member and electrically connected to the plurality of through vias, and upper redistribution wirings provided in at least one upper insulating layer on the sealing member and electrically connected to the buried wirings.