Semiconductor Package Manufacturing Using Carrier Substrate Segmentation
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Solution Overview
Problem
The manufacturing of semiconductor packages faces challenges in achieving compact size, low manufacturing cost, and preventing warpage due to the small size and complex handling of semiconductor chips, as well as difficulties in adhering and testing solder balls and acquiring diversified mount boards.
Innovation Solution
A method involving the formation of a hole in an interconnect substrate, placement of a semiconductor chip, formation of a molding layer, adherence of a carrier substrate with an adhesive layer, and subsequent detachment and removal of the carrier substrates to create a redistribution substrate, which helps in preventing warpage and allowing for easy handling and recycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are made smaller to reduce package size, then compact size is achieved, but handling and testing become more difficult
Solution Approach 1:
A carrier substrate is introduced as an intermediary component to hold multiple semiconductor chips during manufacturing processes. The chips are mounted on the carrier substrate, which provides a stable platform for handling, wiring, and testing operations, thereby solving the difficulty of manipulating small chips directly
Solution Approach 2:
The manufacturing process is segmented into distinct stages: chip mounting on carrier substrate, wiring formation, carrier substrate removal, and final package assembly. This segmentation allows complex operations to be performed on the carrier substrate first, then transferred to the final package structure
2Ease of operation
If carrier substrates are used to facilitate chip handling, then ease of operation is improved, but device complexity increases
Solution Approach 1:
Multiple semiconductor chips are mounted on the carrier substrate and wiring is formed in advance before the carrier substrate is removed. This preliminary action on the carrier substrate simplifies the overall process by providing a stable platform for operations that would be difficult to perform on the final package structure
Solution Approach 2:
The carrier substrate serves as a temporary manufacturing aid that is discarded after its purpose is fulfilled. It is removed after chips are mounted and wired, leaving only the chips and their interconnections in the final package, thereby eliminating the complexity of the carrier substrate from the final product
3Ease of manufacture
If adhesive layers are used to attach carrier substrates, then ease of manufacture is improved, but warpage occurs
Solution Approach 1:
The adhesive layer is applied in segments or at specific locations rather than uniformly across the entire carrier substrate. This segmented application reduces the total adhesive volume and minimizes the warpage-inducing forces while still providing adequate attachment at critical points
Solution Approach 2:
The adhesive application parameters are optimized by controlling the adhesive thickness, composition, and curing conditions. These parameter changes allow the adhesive to provide sufficient bonding strength while minimizing the internal stresses that cause warpage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of compact semiconductor packages with reduced warpage risk, facilitating easy detachment and recycling of carrier substrates, and improves handling and testing of small semiconductor chips.
Implementation Method 1
adhering a second carrier substrate onto the molding layer with an adhesive layer
Data Source
AI summary
A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.