Semiconductor Package Fabrication via Carrier-Supported Thinning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor package fabrication methods face challenges such as wafer cracking during debonding, increased fabrication costs due to bonding entire wafers instead of known good dies, and warpage issues affecting subsequent bonding processes, which hinder the production of miniaturized, high-performance semiconductor packages.

Innovation Solution

The method involves forming a build-up structure on a carrier with conductive pads, disposing a semiconductor chip in a flip-chip manner, forming through holes and bumps for electrical connections, and encapsulating the chip with an electronic element, allowing for direct fabrication on the carrier without debonding the wafer, enabling electrical testing and reducing the overall package thickness while improving yield and heat dissipation through a heat conducting layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the wafer is debonded from the carrier after thinning, then the semiconductor chips can be singulated and stacked, but the wafer is easily cracked due to reduced thickness

Engineering Contradiction:
Improvechip stacking capabilityVSAvoidwafer strength
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The wafer is thinned while still bonded to the carrier, and the thinning process is completed before debonding. This preliminary thinning action while supported by the carrier prevents cracking that would occur if thinning were attempted after debonding, as the carrier provides mechanical support during the vulnerable thinning process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The carrier serves as an intermediary support structure during the wafer thinning process. By keeping the wafer bonded to the carrier during thinning, the carrier acts as a mediator that prevents wafer cracking, allowing the thinning operation to be completed safely before the wafer is debonded for stacking

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the entire wafer is bonded to the carrier instead of known good dies, then the bonding process is simplified, but the overall fabrication cost is increased

Engineering Contradiction:
Improvebonding process simplicityVSAvoidfabrication cost
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The wafer is segmented into individual dies after thinning while on the carrier, and only the known good dies are selected for stacking. This segmentation approach allows rejection of defective dies and reduces material waste, lowering fabrication costs while maintaining simple bonding processes for the good dies

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality levels are applied to different regions of the wafer by performing electrical testing and selecting only known good dies for stacking. This local quality differentiation ensures that only high-quality dies are used in the final product, reducing rework and failure rates, thereby lowering overall fabrication costs

Inventive Principle:
Principle #3Local quality

3Volume of moving object

If the wafer is thinned before stacking, then the package size is reduced, but warpage occurs affecting subsequent bonding processes

Engineering Contradiction:
Improvepackage sizeVSAvoidwafer flatness
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The carrier acts as an intermediary support that maintains wafer flatness during the thinning process. By performing thinning while the wafer is still bonded to the rigid carrier, warpage is prevented, and the wafer remains flat and stable for subsequent stacking and bonding operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The wafer thinning operation is performed as a preliminary action while the wafer is still supported by the carrier. This timing ensures that thinning is completed before the wafer is debonded and stacked, achieving miniaturization while maintaining stability through the carrier support during the critical thinning phase

Inventive Principle:
Principle #10Preliminary action

4Length of moving object

If the wafer is thinned and debonded, then the chip thickness is reduced for miniaturization, but cracking and damage occur during the process

Engineering Contradiction:
Improvechip thicknessVSAvoidchip integrity
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The thinning operation is performed as a preliminary action while the wafer is still bonded to the carrier, which provides mechanical support. This timing ensures that thinning is completed before debonding, achieving miniaturization while preventing cracking and damage that would occur if thinning were attempted after the wafer was standalone

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The carrier serves as an intermediary support structure during the thinning process, preventing chip cracking and damage. By maintaining the wafer-carrier bond during thinning, the carrier absorbs mechanical stresses that would otherwise cause cracking in the thin wafer, ensuring chip integrity throughout the process

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11101235B2Fabrication method of semiconductor package with stacked semiconductor chips
Publication Date: 2021.08.24 SILICONWARE PRECISION IND CO LTD
  • US11101235B2 patent drawing
  • US11101235B2 patent drawing
  • US11101235B2 patent drawing

AI summary

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.