Semiconductor Package Cascode Design for Thermal and Electrical Optimization
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Solution Overview
Problem
Traditional semiconductor packages face issues with high on-resistance due to wirebonds, limited heat dissipation, and large footprint, which hinder device performance.
Innovation Solution
A semiconductor package design featuring a substrate with conductive pads, bidirectional compound semiconductor components, and power MOSFETs arranged in a cascode configuration, with exposed or encapsulated heatsinks for enhanced thermal management and reduced wirebond usage, utilizing III-nitride based bidirectional power semiconductor devices for improved electrical and thermal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonds are used to interconnect electrodes, then electrical connections are established, but on-resistance increases
Solution Approach 1:
The patent removes wirebonds from the interconnection system entirely, replacing them with direct substrate trace connections. This extraction of the problematic wirebond element eliminates the source of high on-resistance while maintaining electrical connectivity through alternative means (substrate traces), directly resolving the contradiction between connection reliability and energy loss.
Solution Approach 2:
The patent replaces the mechanical wirebond system with an integrated substrate trace system. Instead of using separate mechanical wire elements to create connections, the electrical interconnections are formed directly within the substrate plane through conductive traces, substituting a mechanical interconnection approach with an integrated electrical pathway approach that has lower resistance.
2Ease of manufacture
If traditional packaging is used, then device assembly is simplified, but heat dissipation capability is limited
Solution Approach 1:
The patent transitions from conventional single-sided or limited heat dissipation approaches to a dual-sided cooling architecture. Heat sinks are attached to both the top and bottom surfaces of the substrate, utilizing the third dimension (vertical space on both sides) to maximize thermal dissipation area. This dimensional approach to heat management maintains manufacturing simplicity while dramatically improving temperature control.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support for the devices, creates electrical interconnections through its traces, and acts as a thermal management platform with dual-sided heat sinks. This multi-functionality allows the same structural element to address both assembly simplicity and heat dissipation requirements without requiring separate specialized components.
3Ease of manufacture
If conventional device layout is used, then manufacturing is straightforward, but package footprint is large
Solution Approach 1:
The patent merges multiple functional elements into the substrate itself: electrical traces for interconnection, mounting areas for devices, and thermal pathways for heat dissipation. By combining these previously separate functions into a single integrated substrate structure, the package footprint is reduced while maintaining manufacturing straightforwardness through standard substrate fabrication processes.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of components and heat sinks to reduce the horizontal footprint. Devices are mounted on both sides of the substrate, and heat sinks extend vertically from both surfaces, transitioning from a two-dimensional layout to a three-dimensional configuration that minimizes package area while preserving ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces on-resistance, enhances heat dissipation through dual-sided cooling, and minimizes package footprint, thereby improving the overall performance and efficiency of semiconductor devices.
Implementation Method 1
a first heatsink electrically connecting the first power electrode of the first power semiconductor device to the first power electrode of the compound semiconductor component, and a second heatsink electrically connecting the first power electrode of the second power semiconductor device to the second power electrode of the compound semiconductor component. The first heatsink and the second heatsink are preferably thermally coupled to the compound semiconductor component.
Data Source
AI summary
A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.