Semiconductor Package Cavity Channels for Thin PoP Encapsulation
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Solution Overview
Problem
The challenge in semiconductor packaging is to minimize the thickness of package-on-package structures while ensuring efficient encapsulation and electrical connectivity.
Innovation Solution
A semiconductor package design featuring a lower substrate with a semiconductor chip, an upper substrate with protruding structures defining a cavity and channel regions, and a connection structure that reduces joint pitch and secures encapsulant distribution paths, using a connection bump for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the package structure is reduced, then the overall package size is minimized, but the encapsulation quality and flux residue removal become more difficult
Solution Approach 1:
The lower surface of the upper substrate is segmented into multiple protruding structures that divide the encapsulant filling space into distinct cavity and channel regions. This segmentation enables controlled flux residue removal paths while maintaining reduced package thickness, as the channels provide dedicated pathways for encapsulant flow and residue evacuation without increasing overall package height.
Solution Approach 2:
The invention introduces a vertical dimension feature (protruding structures extending downward from the upper substrate) to create three-dimensional cavity and channel regions. This dimensional approach allows flux residue removal and encapsulant distribution to occur in the vertical space between substrates, achieving reliable encapsulation quality without increasing the horizontal footprint or overall package thickness.
2Reliability
If protruding structures are added to the upper substrate, then encapsulant distribution is improved, but device complexity increases
Solution Approach 1:
The protruding structures serve multiple functions simultaneously: they define cavity regions for encapsulant distribution, create channel regions for flux residue removal, and maintain structural support between substrates. This multi-functionality achieves improved encapsulant distribution without proportionally increasing device complexity, as a single structural feature accomplishes multiple objectives.
Solution Approach 2:
The array of protruding structures creates a porous-like configuration with interconnected cavity and channel regions that facilitate encapsulant penetration and flux residue evacuation. This porous structure approach improves encapsulant distribution by allowing fluid flow through multiple pathways while maintaining a relatively simple geometric pattern that can be manufactured using standard PCB techniques.
3Length of moving object
If the joint pitch is reduced, then the package thickness is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The protruding structures are formed on the upper substrate before final assembly, creating pre-defined cavity and channel regions that guide encapsulant flow and flux residue removal. This preliminary structuring establishes alignment references that facilitate precise positioning during assembly, reducing the manufacturing precision burden despite reduced joint pitch between substrates.
Data Source
AI summary
A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.