Semiconductor Package Cavity Layout for Dense Chip Integration and Cooling
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and efficient heat dissipation while maintaining a small form factor, which is essential for miniaturized electronic components in portable devices.
Innovation Solution
A semiconductor package design featuring a first substrate with a cavity, redistribution structures, and multiple chips connected by bridge chips, along with heat dissipation members, to enhance integration and heat dissipation capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are integrated in a compact arrangement to achieve high integration, then the integration capacity increases, but the heat dissipation becomes more difficult
Solution Approach 1:
The patent divides the semiconductor package into multiple functional regions: a cavity region for housing heat-generating chips with dedicated heat dissipation paths, and a flat region for low-profile chips. This segmentation allows different heat management strategies for different chip types, resolving the contradiction between high integration and heat dissipation by organizing chips spatially according to their thermal characteristics.
Solution Approach 2:
The patent utilizes vertical dimension by creating a cavity that extends downward from the substrate, allowing chips to be arranged at different vertical levels. This three-dimensional arrangement increases integration capacity while maintaining thermal management capabilities, as heat can be dissipated vertically through the cavity structure rather than only in the horizontal plane.
2Volume of moving object
If the semiconductor package is miniaturized to reduce volume, then the form factor decreases, but the heat dissipation efficiency deteriorates
Solution Approach 1:
The patent embeds a cavity within the substrate structure, creating a nested configuration where chips are housed inside the cavity rather than on the surface. This nesting approach reduces the overall package volume by utilizing the substrate's internal space while maintaining adequate heat dissipation paths through the cavity's open structure.
Solution Approach 2:
The patent applies different structural qualities to different regions: the cavity region provides enhanced heat dissipation capacity with vertical walls and open space, while the flat region maintains a compact profile. This localized differentiation allows the package to be miniaturized overall while preserving heat dissipation efficiency in critical areas.
3Length of stationary object
If chips are arranged in a flat configuration to reduce package height, then the form factor improves, but the heat dissipation capability decreases
Solution Approach 1:
The patent segments chips into two groups: those placed in the cavity with superior heat dissipation and those placed on the flat region with lower profile. This segmentation allows the package to achieve reduced overall height while maintaining heat dissipation capability for heat-generating components through their specialized cavity placement.
Data Source
AI summary
A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.