Semiconductor Package Cavity Layout for Thin Profile Heat Dissipation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Thermal characteristics of semiconductor packages with stacked semiconductor chips deteriorate as the thickness of the semiconductor chip is reduced, leading to decreased thermal performance.

Innovation Solution

A semiconductor package design that includes a lower substrate with redistribution wirings, a first semiconductor chip with a silicon substrate and activation layer, connecting members, and an upper substrate with through cavities to accommodate the chip, allowing for improved heat dissipation while maintaining the overall thickness of the package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the thickness of the semiconductor chip is reduced, then the overall package thickness can be decreased, but the thermal characteristics deteriorate

Engineering Contradiction:
Improvepackage thicknessVSAvoidthermal characteristics
Core Design Contradiction:
Length of stationary objectVSTemperature

Solution Approach 1:

The patent introduces a through cavity extending through the upper substrate in the vertical dimension, allowing the semiconductor chip to be recessed into the package structure. This dimensional reconfiguration enables the chip thickness to be effectively reduced while maintaining adequate thermal path length through the substrate, resolving the contradiction between package thickness reduction and thermal characteristic preservation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If the thickness of the semiconductor chip is increased to improve thermal characteristics, then the thermal resistance is reduced, but the overall package thickness increases

Engineering Contradiction:
Improvethermal characteristicsVSAvoidpackage thickness
Core Design Contradiction:
TemperatureVSLength of stationary object

Solution Approach 1:

The semiconductor chip is nested within the through cavity of the upper substrate, creating a recessed configuration. This nesting allows the chip to be positioned lower in the package structure, enabling the use of thicker chips for improved thermal characteristics while maintaining a compact overall package thickness by utilizing the vertical space within the cavity

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances thermal characteristics by increasing the thickness of the silicon substrate, reducing the mold gap, and improving heat spreading, thereby maintaining the package's performance and efficiency.

Implementation Method 1

the first semiconductor chip may transfer heat generated from the activation layer to the first surface of the silicon substrate

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The chip redistribution wiring layer may absorb the heat and dissipate it upward

Methodology Applied
Scientific EffectHeat absorption and dissipation: Conduction (thermal)

Data Source

PatentUS20240429146A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2024.12.26 SAMSUNG ELECTRONICS CO LTD
  • US20240429146A1 patent drawing
  • US20240429146A1 patent drawing
  • US20240429146A1 patent drawing

AI summary

A semiconductor package includes a lower substrate that includes a chip mounting region and a peripheral region, where the lower substrate includes lower redistribution wirings; a first semiconductor chip on the chip mounting region, where the first semiconductor chip includes: a silicon substrate that includes a first surface and a second surface that are opposite to each other, an activation layer on the second surface, and a chip redistribution wiring layer that is on the first surface and includes a plurality of chip redistribution wirings that are electrically insulated from the activation layer; a plurality of connecting members that are on the peripheral region and are electrically connected to the lower redistribution wirings; and an upper substrate on the plurality of connecting members, and where at least a portion of the first semiconductor chip is in a through cavity defined by the upper substrate.