Semiconductor Package Cavity Layout for Compact Gate Connections

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density while maintaining short gate connection distances and adequate creepage and clearance distances, which limits package size and thermal contact with heat sinks, especially in large packages.

Innovation Solution

A semiconductor package design featuring a substrate with a semiconductor die, electrical connector, and an encapsulant with a recess exposing the connector, allowing for a printed circuit board to be integrated within the recess, thereby reducing package size and enhancing thermal contact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard lead configurations are used in higher voltage domains, then creepage and clearance distances are maintained, but package size increases

Engineering Contradiction:

Improvecreepage and clearance distancesVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar lead configuration to a three-dimensional cavity structure. The recess/cavity exposes the electrical connector at the bottom surface of the encapsulant, utilizing the vertical dimension to achieve adequate creepage and clearance distances without increasing the horizontal package footprint. This dimensional change allows compact packaging while maintaining electrical safety distances.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If integration density is increased, then area on printed circuit board is reduced, but distance between gate connection and gate driver increases

Engineering Contradiction:

Improveprinted circuit board areaVSAvoiddistance between gate connection and gate driver

Core Design Contradiction:

Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent implements nesting by placing the gate driver die directly on the bottom surface of the recess/cavity, which already houses the exposed electrical connector. This nested arrangement minimizes the distance between the gate connection (electrical connector) and the gate driver, allowing high integration density on the printed circuit board without sacrificing signal performance.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Quantity of substance

If package size is increased for large packages, then integration capacity is improved, but thermal contact with heat sink deteriorates due to package bow

Engineering Contradiction:

Improveintegration capacityVSAvoidthermal contact with heat sink

Core Design Contradiction:

Quantity of substanceVSTemperature

Solution Approach 1:

The patent applies local quality by creating a recess/cavity in a specific location of the encapsulant where thermal contact is critical. The exposed electrical connector at the bottom surface of the recess provides a localized area for direct thermal and electrical connection to the heat sink, ensuring efficient heat dissipation in the critical region without compromising overall integration capacity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12506051B2Semiconductor package comprising a cavity with exposed contacts and a semiconductor module

Publication Date: 2025.12.23 INFINEON TECH AUSTRIA AG

AI summary

A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.