Semiconductor Package Structure for CDM ESD Suppression

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Solution Overview

Problem

Existing semiconductor devices are prone to electrostatic destruction due to the charged device model (CDM), especially during mounting on substrates, which can lead to reliability issues in memory systems.

Innovation Solution

The semiconductor device incorporates a rewiring board with embedded wirings, a semiconductor chip, and additional structures that increase the height of the device, creating a greater distance between the device and mounting trays, thereby reducing electrostatic capacitance and preventing CDM-induced damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the semiconductor device is mounted close to the mounting tray, then the mounting process is simple and compact, but the device is prone to electrostatic destruction due to CDM

Engineering Contradiction:
Improveelectrostatic destruction resistanceVSAvoiddevice structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a support structure that extends in the vertical dimension (height direction) from the mounting surface. This support structure raises the semiconductor chip to a higher position, increasing the distance between the chip and the mounting tray. By utilizing the vertical dimension, the patent effectively increases spacing without expanding the horizontal footprint, thus preventing CDM while maintaining a compact overall device layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the distance between the semiconductor device and mounting tray is increased, then CDM is suppressed, but the device height and complexity increase

Engineering Contradiction:
Improveelectrostatic destruction resistanceVSAvoiddevice height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent divides the support function into separate modular components: a mounting surface, a support structure with specific geometric features (such as pillars or raised regions), and the semiconductor chip. This segmentation allows the support structure to be independently designed and optimized for electrostatic protection without affecting other device functions. The modular approach enables flexible configuration to achieve the required height while controlling overall device complexity.

Inventive Principle:
Principle #1Segmentation

3Reliability

If additional support structures are added to increase device height, then CDM protection is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrostatic destruction resistanceVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent integrates the support structure directly into the mounting substrate or housing as a unified component rather than adding it as a separate assembly step. The support structure may be formed as an integrated feature during substrate fabrication or molding processes, combining the mounting function and support function into a single manufacturing operation. This merging approach maintains manufacturing simplicity while achieving the required height increase for CDM protection.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of both the semiconductor device and the memory system by effectively suppressing electrostatic destruction due to CDM, while also improving heat dissipation and reducing signal loss.

Implementation Method 1

creating a greater distance between the device and mounting trays, thereby reducing electrostatic capacitance and preventing CDM-induced damage

Methodology Applied
Scientific EffectElectrostatic capacitance reduction: Capacitance

Data Source

PatentUS20250167114A1Semiconductor device and memory system
Publication Date: 2025.05.22 KIOXIA CORP
  • US20250167114A1 patent drawing
  • US20250167114A1 patent drawing
  • US20250167114A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first substrate; a semiconductor chip provided in a first region of a first face of the first substrate; and a first structure provided in a second region of the first face, wherein the first substrate includes: wiring embedded in the first substrate; a first conductor coupled to the semiconductor chip and the wiring and exposed on the first face; and a second conductor coupled to the first conductor via the wiring and exposed on a second face of the first substrate, a height of the first structure in a first direction perpendicular to the first face is greater than a height of the semiconductor chip in the first direction, in a case where the first face is taken as a reference.