Semiconductor Package Substrate for Flexible Memory Channel Mapping
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently accommodating various channel configurations of stacked memory chips without requiring multiple substrate designs, leading to increased fabrication costs and complex electrical connections.
Innovation Solution
A semiconductor package design featuring a universal package substrate that supports multiple channel configurations through a single configuration, utilizing a conductive connection member to selectively connect power and wire pads externally, allowing the control chip to recognize channel numbers based on voltage application, and employing a flip-chip method for improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple substrate designs are used to accommodate various channel configurations of stacked memory chips, then adaptability to different channel numbers is improved, but device complexity and fabrication costs increase
Solution Approach 1:
The package substrate is designed with a universal configuration that can accommodate multiple channel numbers (2-channel, 4-channel, 8-channel) through a single design. The substrate includes multiple power pads and wire pads that can be selectively connected to memory chips in the stack structure, allowing the same substrate to support different channel configurations without requiring multiple specialized substrate designs.
Solution Approach 2:
The package substrate incorporates dynamic connectivity through selective electrical connections between pads and memory chip terminals. The control chip receives channel number information and dynamically configures the electrical connections to match the required channel configuration, enabling the substrate to adapt its functionality based on the stacked memory chip configuration.
2Adaptability or versatility
If multiple substrate designs are used to accommodate various channel configurations, then adaptability is improved, but fabrication costs increase
Solution Approach 1:
A single universal package substrate design is used for all channel configurations (2-channel, 4-channel, 8-channel), eliminating the need to manufacture multiple different substrate types. This universal substrate includes all necessary power pads and wire pads that can be selectively activated depending on the channel configuration, significantly reducing fabrication costs by standardizing the substrate manufacturing process.
3Adaptability or versatility
If complex electrical connections are used to support various channel configurations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The control chip acts as an intermediary that manages the electrical connections between the package substrate and stacked memory chips. It receives channel number information and configures the electrical connections accordingly, simplifying the overall system by centralizing the control logic in the chip rather than requiring complex fixed wiring for all possible configurations.
Solution Approach 2:
The electrical connections are designed to be dynamically configurable based on the channel number. The package substrate includes multiple power pads and wire pads that can be selectively connected to different memory chip terminals, allowing the electrical connection topology to change dynamically to match the required channel configuration without physical reconfiguration.
Data Source
AI summary
A semiconductor package includes a package substrate having opposing first and second surfaces, a control chip on the first surface, a mode selection connection terminal between the control chip and the package substrate, a stack structure comprising stacked memory chips spaced apart from the control chip on the first surface, a first power pad and a wire pad that are spaced apart at the first surface, a first external connection terminal on the second surface, and first and second interconnection lines in the package substrate. The first power pad and the wire pad are spaced apart from the control chip. The first interconnection line connects the first power pad to the first external connection terminal. The second interconnection line connects the wire pad to the mode selection connection terminal. The first external connection terminal is configured to provide a ground voltage or a power voltage.