Semiconductor Package Layout for Chip Alignment and Short-Circuit Prevention
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Solution Overview
Problem
Existing semiconductor packages face challenges in minimizing defects and improving reliability, particularly in the connection and alignment of substrates and semiconductor chips, which can lead to electric short circuits and misalignment.
Innovation Solution
A semiconductor package design that includes a first substrate, a second substrate, a semiconductor chip, solder structures, and bumps or supporting patterns to ensure precise alignment and electrical connectivity, with guide patterns and under-fill layers to prevent misalignment and short circuits during reflow processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If solder structures are placed close to the semiconductor chip for compact design, then device complexity is reduced, but the risk of electric short circuits increases
Solution Approach 1:
The patent introduces an under-fill layer as an intermediary substance between the solder structures and the semiconductor chip. This under-fill layer physically separates the solder structures from the chip, preventing direct contact that could cause short circuits, while still allowing the solder structures to provide electrical connection and mechanical support functions.
Solution Approach 2:
The patent segments the connection structures by introducing guide patterns that are spatially separated from the semiconductor chip. The guide patterns form distinct regions that guide solder structures along predetermined paths, ensuring that solder structures remain separated from the chip body while maintaining electrical connectivity through controlled locations.
2Manufacturing precision
If guide patterns are added to prevent misalignment during reflow, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The guide patterns are formed in advance on the substrate before the reflow process. These pre-formed patterns serve as alignment guides that direct the placement and flow of solder structures, ensuring precise positioning without requiring complex real-time alignment mechanisms during the reflow process.
Solution Approach 2:
The guide patterns act as intermediary structures that mediate between the solder structures and the semiconductor chip. They provide a predetermined path and positioning reference for the solder structures, ensuring accurate alignment while being simple planar features that add minimal structural complexity.
3Reliability
If supporting patterns are used to maintain gap distance, then reliability is improved, but ease of manufacture decreases
Solution Approach 1:
The supporting patterns are merged with the guide patterns into a single integrated pattern layer. Both functions (guiding solder structures and maintaining gap distance) are achieved through the same set of planar features formed in the same fabrication step, eliminating the need for separate supporting structures and simplifying the manufacturing process.
Solution Approach 2:
The guide patterns serve multiple functions: they guide the placement and flow of solder structures, maintain predetermined gap distances from the semiconductor chip, and provide alignment references. This multi-functionality eliminates the need for separate dedicated supporting structures, simplifying fabrication while ensuring reliable gap maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances reliability by preventing electric short circuits and misalignment, allowing for efficient solder structure formation and maintaining consistent gap distances, thereby improving the overall performance and integrity of the semiconductor package.
Implementation Method 1
each of the solder structures includes a lower solder ball provided on an upper surface of the first substrate, and an upper solder ball provided on a lower surface of the second substrate and reflow joined to the lower solder ball
Data Source
AI summary
A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.