Semiconductor Package Multi-Layer Chip Pad Design
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Solution Overview
Problem
Semiconductor packages face challenges in achieving higher reliability and economic feasibility while meeting consumer demands for superior performance and cost-effectiveness, particularly in terms of integration and durability.
Innovation Solution
A semiconductor package design featuring a circuit substrate with first and second circuit patterns, vias, and a chip pad structure, where the first circuit patterns are perpendicular and spaced apart, and a protection structure with a passivation pattern and photoreactive soluble pattern, enabling robust electrical connections and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip pad is made thinner to reduce chip size, then manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from a single-layer chip pad structure to a multi-layer stacked structure comprising a first chip pad layer, second chip pad layer, and third chip pad layer. This dimensional expansion in the vertical direction allows each individual layer to maintain sufficient thickness for manufacturing precision while achieving an overall reduced chip profile through layered stacking, directly resolving the contradiction between thinning the chip pad and maintaining manufacturing precision.
2Productivity
If circuit patterns are made narrower to increase integration, then reliability of electrical connections deteriorates
Solution Approach 1:
The patent employs a composite multi-layer pad structure where each layer can be composed of different materials optimized for specific functions. This composite approach allows narrow circuit patterns to maintain reliable electrical connections by distributing the connection function across multiple specialized layers, thereby resolving the contradiction between increasing integration density and maintaining connection reliability.
3Reliability
If the number of vias is increased to improve electrical connectivity, then device complexity increases
Solution Approach 1:
The patent segments the via structure into multiple distinct via layers (first via layer, second via layer, third via layer) that are distributed across different vertical levels. This segmentation allows electrical connectivity to be established through multiple pathways without requiring an excessive number of vias in a single plane, thereby improving connectivity reliability while managing device complexity through organized spatial distribution.
4Reliability
If protection structures are added to prevent damage during assembly, then manufacturing process complexity increases
Solution Approach 1:
The patent incorporates protection structures as integral components during the preliminary stages of chip fabrication, rather than adding them as separate post-processing steps. The multi-layer pad structure itself provides inherent mechanical protection, and protection layers are formed concurrently with other chip structures during standard fabrication processes, thereby achieving damage prevention without significantly increasing manufacturing process complexity.
Data Source
AI summary
Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.