Semiconductor Package Wiring via Chip Rotation
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high capacity and thin form factors due to the complexity of internal wiring and potential defects during bonding wire formation when semiconductor chips are stacked or placed side by side, which affects the reliability and performance of mobile devices.
Innovation Solution
The semiconductor package design includes four semiconductor chips (two pairs) where each pair is connected as a single chip using internal wiring, allowing for a simpler wiring structure and reduced thickness by rotating the chips relative to each other on the package base substrate, thereby preventing defects and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked or placed side by side to increase capacity, then the quantity of substance (chip capacity) is improved, but the device complexity (internal wiring complexity) worsens
Solution Approach 1:
The semiconductor chip is divided into multiple segments (first chip segment, second chip segment, third chip segment) arranged in a specific pattern. This segmentation allows each segment to be independently connected to bonding pads, reducing the overall wiring complexity while maintaining high capacity through the combined functionality of all segments.
Solution Approach 2:
The chip segments are arranged in a two-dimensional layout rather than being stacked vertically or connected in a linear fashion. This dimensional arrangement optimizes the connection paths to bonding pads, reducing wire length and complexity while achieving high capacity through parallel operation of multiple segments.
2Length of stationary object
If semiconductor chips are stacked to reduce package thickness, then the length (package thickness) is improved, but the reliability (bonding wire defects) worsens
Solution Approach 1:
Instead of stacking chips vertically which requires long bonding wires, the chip is segmented and arranged horizontally with each segment connected to nearby bonding pads. This eliminates the need for long vertical bonding wires, reducing the risk of defects while achieving thin package profile through optimized horizontal layout.
Solution Approach 2:
The patent replaces traditional vertical stacking with mechanical bonding wires with a planar segmentation approach where chip segments are directly connected to bonding pads through shorter, more reliable pathways. This substitution of the mechanical bonding system with an optimized layout reduces bonding wire length and associated defects.
3Device complexity
If chip segments are arranged to reduce wiring complexity, then the device complexity (wiring structure) is improved, but the area (chip layout space) worsens
Solution Approach 1:
The chip segments are arranged in an asymmetric pattern optimized for wiring efficiency rather than a symmetric layout. The first, second, and third chip segments are positioned to minimize wire lengths to their respective bonding pads, achieving reduced wiring complexity without requiring excessive layout area through careful asymmetric placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and performance of semiconductor packages by reducing thickness, simplifying internal wiring, and preventing defects during bonding wire formation, resulting in a smaller, lighter, and higher-capacity electronic device.
Implementation Method 1
a bonding wire electrically connecting the chip pad and the bonding pad to each other
Data Source
AI summary
A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.