Semiconductor Package Coating Layer Void Prevention
Solution Overview
Problem
Conventional flip chip semiconductor packages face reliability issues due to voids in the underfill member between the semiconductor chip and the printed circuit board, which can lead to moisture leakage and cracking, especially as the size of the bump connecting the bonding pads decreases, making it difficult to fill the underfill material effectively.
Innovation Solution
A semiconductor package design that includes a coating layer on the substrate and semiconductor chip, with an underfill member filled over this layer, using hydrophilic or hydrophobic materials to prevent void formation by ensuring the underfill material can be easily filled in the narrow gap, and the coating layer is formed using processes like vacuum deposition or spin coating to cover exposed surfaces, including bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the size of the bump is decreased to match the reduced bonding pad size, then the semiconductor package can accommodate higher density bonding pads, but the gap between the semiconductor chip and the printed circuit board becomes too small to effectively fill with underfill material
Solution Approach 1:
A coating layer is formed on the semiconductor chip and printed circuit board surfaces before the underfill material is applied. This preliminary coating action modifies the surface properties to enhance wetting and facilitate complete filling of the narrow gap, resolving the contradiction between small bump size and effective underfill material application
2Volume of moving object
If the gap between the semiconductor chip and the printed circuit board is decreased, then the package size is reduced, but voids are likely to be created in the underfill member making it difficult to fill completely
Solution Approach 1:
The surface energy parameters of the substrate are modified by applying a coating layer with specific wetting properties. This parameter change enables the underfill material to completely fill the reduced gap without forming voids, maintaining reliability while achieving compact package size
3Ease of manufacture
If voids are created in the underfill member, then the filling process may be simpler, but moisture can leak into the voids inducing cracks that are detrimental to the underfill member
Solution Approach 1:
The coating layer is designed to control the wetting behavior of the underfill material, converting the potential harm of void formation into complete gap filling. The hydrophilic or hydrophobic properties of the coating layer guide the underfill material to flow completely into the gap, eliminating voids that would otherwise lead to moisture ingress and cracking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the semiconductor package by preventing voids and moisture ingress, thereby improving the structural integrity against external shocks and vibrations, and ensuring effective filling of the underfill material in the narrow gap between the chip and the substrate.
Implementation Method 1
the coating layer is formed using processes like vacuum deposition or spin coating to cover exposed surfaces, including bumps
Implementation Method 2
the coating layer is formed using processes like vacuum deposition or spin coating to cover exposed surfaces, including bumps
Implementation Method 3
using hydrophilic or hydrophobic materials to prevent void formation by ensuring the underfill material can be easily filled in the narrow gap
Data Source
AI summary
A semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate having connection pads formed on one surface thereof, a semiconductor chip having bonding pads formed on one surface thereof to correspond to the connection pads; bumps for electrically connecting the connection pads and the bonding pads with each other, a coating layer located on exposed surface portions of the bonding pads and the connection pads to prevent voids from being formed in spaces between the substrate and the semiconductor chip, and an underfill member filled in the spaces over the coating layer.